The Design and Verification Conference & Exhibition Europe (DVCon Europe) is is a new technical conference in Europe targeting the application of languages, tools and intellectual property for the design and verification of electronic systems and integrated circuits. Sponsored by Accellera Systems Initiative, DVCon Europe brings chip architects, systems designers, software developers and IP integrators the latest methodologies, techniques, applications and demonstrations on the practical use of EDA and IP languages and standards used in electronic design.
This call for tutorial abstracts solicits tutorials that are highly technical and reflect real life experiences in using languages, standards, methods and Electronic Design Automation (EDA) tools. Tutorial submissions are encouraged in (but not restricted to) the following areas:
The application of system-level design and verification languages such as SystemC, SystemVerilog or e
The use of SystemVerilog Assertions (SVA) or the Property Specification Language (PSL)
Verification methodologies based on the Universal Verification Methodology (UVM)
IP reuse, automation and integration standards based on IP-XACT
Low power design and verification using the Unified Power Format (UPF)
Tutorial submission closes May 8, 2014.
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