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tyler

2d array data passing through generic payload

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I tried to pass a 2d array of data through the generic payload.

 

    int a[10][10];

    trans.set_data_ptr((unsigned char*) a);

...

...

    unsigned char* data = trans.get_data_ptr;

Then if i get the data ptr at my target, I would have a 1d array. I guess this is not doable here.

I wonder what if I use the tlm extension to add a customized extension to generic payload, and have a local 2d array there and I have access it through the generic payload instance?

Can i write a method in extension class that takes a 2d array as a argument and then assign it to the local one so i can manipulate it at my initiator and a method that would return it so that i can get it at my target?

Thank you in advance for any clarification and time. T

 

 

 

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TLM payload is used for untyped raw data transfers. Data format is usually a property of device. 

Let's consider an example:  Initiator is CPU model, and target is Convolution filter accelerator. Accelerator accepts a 2d matrix (2d array) of coefficients as an input.  Documentation of accelerator must specify a binary format of data, for example:  coefficients are stored in row-major order, each coefficient is 8-byte signed integer.

Using this documentation initiator converts 2d array into a raw data of tlm payload. And device model converts raw data back into 2d array. This is how it is usually done.

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12 hours ago, Roman Popov said:

TLM payload is used for untyped raw data transfers. Data format is usually a property of device. 

Let's consider an example:  Initiator is CPU model, and target is Convolution filter accelerator. Accelerator accepts a 2d matrix (2d array) of coefficients as an input.  Documentation of accelerator must specify a binary format of data, for example:  coefficients are stored in row-major order, each coefficient is 8-byte signed integer.

Using this documentation initiator converts 2d array into a raw data of tlm payload. And device model converts raw data back into 2d array. This is how it is usually done.

Thank you Roman for helping!

I am confused because TLM and systemc set lots of rules and standards, but it didn't say what can not be done by using c++. 

For example, can I inherit the payload interface and make my own payload class with stuffs I need and pass it through the nb_transport call. Would this make sense to you? 

Also, in the nb_transport, time is annotated by passing the delay with the trans object, how could I actually have a clock and have all the transactions follow the clock edge? I tried to use sc_method, but somewhere in the LRM says generic payload only works with sc_thread. Without the clock, how are the signals traced? If a bug or more bugs in the design, how could I debug it systematically? Back to RTL i would look at my simulation waveforms, but how to solve it under the systemc and tlm abstraction level?

Thanks again!

Best,

Tyler

 

Thanks again!

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50 minutes ago, tyler said:

Thank you Roman for helping!

I am confused because TLM and systemc set lots of rules and standards, but it didn't say what can not be done by using c++. 

For example, can I inherit the payload interface and make my own payload class with stuffs I need and pass it through the nb_transport call. Would this make sense to you? 

Those questions are covered in detail in paragraphs 14.1 and 14.2 of SystemC standard.  Can't answer in a better way.

Quote

Also, in the nb_transport, time is annotated by passing the delay with the trans object, how could I actually have a clock and have all the transactions follow the clock edge? I tried to use sc_method, but somewhere in the LRM says generic payload only works with sc_thread. Without the clock, how are the signals traced? If a bug or more bugs in the design, how could I debug it systematically? Back to RTL i would look at my simulation waveforms, but how to solve it under the systemc and tlm abstraction level?

TLM2.0 simulations are not cycle-accurate, so you don't have clock edge events.  In AT modeling style you should call wait(delay) after each transport call.  In LT modeling style all initiators are temporaly decoupled and can run ahead of simulation time, usually for a globally specified time quantum. 

For debugging you can use the same techinques as in cycle-accurate modeling:

  • Source-level debugging with breakpoints and stepping
  • Transaction and signal tracing
  • Logging

Comparing with RTL, debugging using waveform won't be that effective, because in AT/LT modeling state of model can change significantly in a single simulator/waveform step.  Usually preffered way is combination of logging and source-level debug. Debugging TLM models is harder comparing to RTL. Also C++ is much more complex and error-prone comparing to VHDL/Verilog. 

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