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  1. Thank you Roman for helping! I am confused because TLM and systemc set lots of rules and standards, but it didn't say what can not be done by using c++. For example, can I inherit the payload interface and make my own payload class with stuffs I need and pass it through the nb_transport call. Would this make sense to you? Also, in the nb_transport, time is annotated by passing the delay with the trans object, how could I actually have a clock and have all the transactions follow the clock edge? I tried to use sc_method, but somewhere in the LRM says generic payload only works with sc_thread. Without the clock, how are the signals traced? If a bug or more bugs in the design, how could I debug it systematically? Back to RTL i would look at my simulation waveforms, but how to solve it under the systemc and tlm abstraction level? Thanks again! Best, Tyler Thanks again!
  2. I tried to pass a 2d array of data through the generic payload. int a[10][10]; trans.set_data_ptr((unsigned char*) a); ... ... unsigned char* data = trans.get_data_ptr; Then if i get the data ptr at my target, I would have a 1d array. I guess this is not doable here. I wonder what if I use the tlm extension to add a customized extension to generic payload, and have a local 2d array there and I have access it through the generic payload instance? Can i write a method in extension class that takes a 2d array as a argument and then assign it to the local one so i can manipulate it at my initiator and a method that would return it so that i can get it at my target? Thank you in advance for any clarification and time. T
  3. thank you sir for your help. I am trying to use tlm as not only just a bus simulator, i am trying to build systems upon it with systemc as well. What do you think tlm2.0 can achieve in such level? It works simple and easy with buses. But could be more complex with other things.
  4. This is interesting as I have written something to test it myself. The following is 1st transaction, and the 2nd transaction is similar except will have delay of 10ns and address = 2. After I parsed this to nb_transport, my address 1 is lost, and only address 2 remains, and as a matter of fact, anything from the later transaction but sent first would be overwritten by the 2nd one that ends early. I am using peq_with_cb_and_phase. I am not sure why, but i am writting my code based on the LRM address = 1; en = 1; rw = 0; wait(); sc_core::sc_time start_time; tlm::tlm_generic_payload* trans; tlm::tlm_phase phase; sc_core::sc_time delay = sc_time (30, SC_NS); trans = m_mm.allocate(); trans->acquire(); trans->set_command(rw ? tlm::TLM_READ_COMMAND : tlm::TLM_WRITE_COMMAND); trans->set_address(address); trans->set_response_status(tlm::TLM_INCOMPLETE_RESPONSE);
  5. Thanks Roman. I indeed thought of those cases. I currently saw the nonblocking interface uses a queue(fifo) to save the transactions which would make them execute in order in this case. Maybe I should explore more of how to do what you are saying using tlm2.0. That would be something really interesting to know, and it also makes tlm2.0 fancier.
  6. Thank you Eyck for the explanation. Lets take the 2 in parallel transaction for example. Say for nonblocking transport, both 1st and 2nd transactions can happen at 0ns, and each one takes 10ns(1cycle) to finish. So their end point would be 10ns and 20ns respectively. If i were to use blocking transport, I would sent 1st transaction at 0 and wait it finish,and send the 2nd one at 10ns, and wait it to finish at 20ns. This would appear more like a real world example to me since as I were thinking, no one would send two instructions in parallel over one port. A pipelined structure would output based on every cycle and lets just put the cycle as 10ns here in this example, the blocking transport would be more suited and the timing could as well be precise. My initiator would output the transaction every cycle(pipelined module). I guess I am saying the nonblocking transport can do is to make two transactions happen at the same time but end at different times over the blocking transport which seems unclear to me what is the use of this. Think in another way if someone argues that maybe in real module there could be cases where the top module have two or more outputs which would happen at the same time, and the bottom module would take these two as inputs at the same time but process them in a pipelined order, this would be the only use case of denoting the starting point of the transactions. But then the bottom block is stalled for at least one cycle because the top module gives 2 transactions in parallel but the bot block can only process 1 every cycle. Best, Tyler
  7. Hi all, I recently start to study systemC TLM2.0 for AT modeling. As a major AT concept, the non-blocking interface is used. I am very confused in this non-blocking concept as the interface barely defines 4 enums as different phases. The LRM explains them in a very theoretical way but I am confused that why we need the four phases. What makes the four phases so important for modeling ? 0,1,2,3 can be states, handshakes, sync points, whatever, but it is not very clearly said to me. Sync points maybe, but why 4? no more wait() to advance the time, the time is advanced in different phases and based on the protocol. But the time is advanced, and blocking can advance the time as well, the only difference here is the phase. So why adding a phase makes a call nonblocking? The transaction items are just put into a queue to wait. It is blocked in the queue in the target instead of the initiator now. Could someone give a real example about when a non-blocking is a must over the blocking transport? As many are saying that non-blocking is majorly used to model pipeline structure without stalling the owner process, but blocking interface somehow can do the same. The nonblocking transfer can indeed initiate two transactions to, for example , a memory chip, at the same time, say, 0ns;while the blocking has to wait for the first one to finish. However, in the real world, the instructions are cycle based. No one would send out two instructions at the same time over one port. If they do, there are more than one port for access. Blocking interface can have multiple ports too. Please help me with some other real cases that a nonblocking interface has practical meaning to a hardware structure. Enlighten me on this please as I am scratching my head right now. I thought of some types of instructions from cpu to access sram and dram at the same time, but this can be done by blocking as well because it would use multiple sockets. I read the LRM many times and other resources. no one seems to give very clear explanation. I am new so please help! Thanks in advance.
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