isbelen

Vector of modules errors

3 posts in this topic

Hi,

I am pretty new to systemc, and I am trying for days to instantiate an array of modules; but I am not being successfull using sc_vector.

Here is the code:

submodule.h

#ifndef __SUBMODULE_h
#define __SUBMODULE_h

#include <systemc.h>

//------------ DEFINITIONS ---------------------------------
#define BYTE 8
typedef sc_uint<2*BYTE> uint_16b;
typedef sc_uint<BYTE> uint_8b;

//------------ PARAMETERS ----------------------------------
#define MAX_COUNT1 6
#define MAX_COUNT2 4
#define RESET_VALUE false

//------------ MODULE --------------------------------------
template <int N>
class SUBMODULE : public sc_module {
public:
    //------------ Ports -----------------------------------
    sc_in_clk                        i_clk;
    sc_in<bool>                        i_rst;
    sc_in<bool>                        i_en;
    sc_vector< sc_out<uint_16b> >    o_data;
    sc_out<bool>                    o_finish;

    //------------ Variables -------------------------------
    uint_8b                         v_state;
    uint_8b                         v_count1;
    uint_8b                         v_count2;

    //------------ Process ---------------------------------
    void p_main(void) {
        if (i_rst.read()){
            v_state = 0;
            v_count1 = 0;
            v_count2 = 0;
            for(int i = 0; i < N; i++)    o_data[i] = 0;
        }
        else{
            if(i_en.read()){
                switch(v_state){
                    case 0:
                        for(int i = 0; i < N; i++)    o_data[i] = 0;
                        if (MAX_COUNT1 > 0) v_state = 1;
                        else v_state = 2;
                        break;
                    case 1:
                        v_count1++;
                        if(!(v_count1 < MAX_COUNT1))
                            v_state = 2;
                        break;
                    case 2:
                        if(v_count2 < MAX_COUNT2)
                            for(int i = 0; i < N; i++)    o_data[i] = (uint_16b)(100/MAX_COUNT2*(v_count2+1));
                        v_count2++;
                        if(!(v_count2 < MAX_COUNT2)){
                            for(int i = 0; i < N; i++)    o_data[i] = 100;
                            v_state = 3;
                        }
                        break;
                    case 3:
                        if (!RESET_VALUE)
                            for(int i = 0; i < N; i++)    o_data[i] = 0;
                        o_finish = 1;
                        break;
                    default:
                        break;
                }
            }
            else{
                v_state = 0;
                v_count1 = 0;
                v_count2 = 0;
            }
        }
    }

    //------------ Constructor -----------------------------
    SC_HAS_PROCESS(SUBMODULE);
    SUBMODULE(sc_module_name name_) : sc_module(name_), o_data("o_data", N){
        SC_METHOD(p_main);
        for (int j = 0; j < N; j++)
            sensitive << i_clk.pos() << i_rst;
    }
};

#endif

topmodule.h

#ifndef __TOPMODULE_h
#define __TOPMODULE_h

#include <systemc.h>
#include "SUBMODULE.h"

#define MAX_N 8

template <int N>
class TOPMODULE : public sc_module {
public:
	//------------ General Data ----------------------------

	//------------ Ports -----------------------------------
	sc_in_clk						i_clk;
	sc_in<bool>						i_rst;
	sc_in<uint_8b>					i_type;
	sc_vector< sc_out<uint_16b> >	o_data;

	//------------ Signals ---------------------------------
	sc_signal<bool>					s_en;
	sc_signal<bool>					s_finish[N];

	//------------ Variables -------------------------------

	//------------ Components ------------------------------
	sc_vector<SUBMODULE<N> > SM;

	//------------ Methods ---------------------------------


	//------------ Process ---------------------------------
	void p_main(void) {
		if (i_rst.read()){

		}
		else{

		}
	}

	//------------ Constructor -----------------------------
	SC_HAS_PROCESS(TOPMODULE);
	TOPMODULE(sc_module_name name_) : sc_module(name_), SM("SM",N){

		for (int i = 0; i < N; i++){
			SM[i].i_clk(i_clk);
			SM[i].i_rst(i_rst);
			SM[i].i_en(s_en);
			SM[i].o_finish(s_finish[i]);
			SM[i].o_data(o_data[i]);
		}

		SC_METHOD(p_main);
		sensitive << i_clk.pos() << i_rst;
	}
};

#endif

TOPMODULE_tbm.cpp

#include <systemc.h>
#include "TOPMODULE.h"

#define MIN_PERIOD 5

void debug(sc_trace_file* tf, TOPMODULE<MAX_N> *dut){

	sc_trace(tf, dut->i_clk, "i_clk");
	sc_trace(tf, dut->i_rst, "i_rst");
	sc_trace(tf, dut->i_type, "i_en");
	for (int i = 0; i < MAX_N; i++){
		char str[16];
		sprintf(str, "%d", i);
		sc_trace(tf, dut->o_data[i], "o_data_" + std::string(str));
	}

}

int sc_main (int argc, char* argv[]) {

	sc_clock clk ("my_clock",MIN_PERIOD,0.5);
	sc_signal<bool>   rst;
	sc_signal<uint_16b> data[MAX_N];
	sc_signal<uint_8b> type;

	 // Connect the DUT
	TOPMODULE<MAX_N>  dut("dut");

	dut.i_clk(clk);
	dut.i_rst(rst);
	dut.i_type(type);
	for (int i = 0; i < MAX_N; i++)
		dut.o_data[i](data[i]);

	// Open VCD file
	sc_trace_file *wf = sc_create_vcd_trace_file("SM_waveform");
	debug(wf, &dut);

	//TODO
	// Test

	// End Test
	sc_close_vcd_trace_file(wf);

	return 0;// Terminate simulation
}

The error code I get is:

Quote

In file included from C:/Xilinx/Vivado_HLS/2017.1/win64/tools/systemc/include/systemc:117:0,
                 from C:/Xilinx/Vivado_HLS/2017.1/win64/tools/systemc/include/systemc.h:244,
                 from ../../../../src_hls/TOPMODULE_tbm.cpp:1:
C:/Xilinx/Vivado_HLS/2017.1/win64/tools/systemc/include/sysc/utils/sc_vector.h: In member function 'sc_core::sc_vector<T>::iterator sc_core::sc_vector<T>::operator()(ArgumentContainer&) [with ArgumentContainer = sc_core::sc_out<sc_dt::sc_uint<16> >, T = sc_core::sc_out<sc_dt::sc_uint<16> >, sc_core::sc_vector<T>::iterator = sc_core::sc_vector_iter<sc_core::sc_out<sc_dt::sc_uint<16> >, sc_core::sc_direct_access<sc_core::sc_out<sc_dt::sc_uint<16> > > >]':
../../../../src_hls/TOPMODULE.h:51:4:   instantiated from 'TOPMODULE<N>::TOPMODULE(sc_core::sc_module_name) [with int N = 8]'
../../../../src_hls/TOPMODULE_tbm.cpp:27:29:   instantiated from here
C:/Xilinx/Vivado_HLS/2017.1/win64/tools/systemc/include/sysc/utils/sc_vector.h:434:45: error: 'class sc_core::sc_out<sc_dt::sc_uint<16> >' has no member named 'begin'
C:/Xilinx/Vivado_HLS/2017.1/win64/tools/systemc/include/sysc/utils/sc_vector.h:434:45: error: 'class sc_core::sc_out<sc_dt::sc_uint<16> >' has no member named 'end'
make: *** [obj/PatternGenerator_tbm.o] Error 1

Any help?

I tried also with

sc_assemble_vector( SM, &SUBMODULE::o_data).bind( o_data )

but this also does not work.

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You see at least two bugs in your code:

        for (int i = 0; i < N; i++){
            SM[i].i_clk(i_clk);
            SM[i].i_rst(i_rst);
            SM[i].i_en(s_en);
            SM[i].o_finish(s_finish[i]);
            SM[i].o_data(o_data[i]);  // <<< here you forgot subscript operator :  SM[i].o_data[i](o_data[i]);
        }

 

I also recommend to use .at(N) instead of [N] during elaboration since it does bounds checking. Performance is not an issue during elaboration, since it is done once.

 

In a TOPMODULE you've forgotten to initialize o_data

    sc_vector< sc_out<uint_16b> >	o_data;  // Not initialized in TOPMODULE constructor

 

If you can use C++11, I recommend using in-class initializers, since they are more readable, like :

...
    sc_in_clk                       i_clk {"i_clk"};
    sc_in<bool>                     i_rst {"i_rst"};
    sc_in<uint_8b>                  i_type {"i_type"};
    sc_vector< sc_out<uint_16b> >   o_data {"o_data", N};
...

 

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Hi Roman,

Thank you very much, it looks so obvious now. I guess I've just got frustrated.

Unfortunatelly, I can not use C++11 because of compatibility with other projects.

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