gilazilla Posted September 22, 2011 Report Share Posted September 22, 2011 Hi All, I have a question about clocking. I want to achieve "result 2".(see attachment) However i am having problem getting the correct system verilog to work. I have no idea why it did not as expected. I keep on getting result 1 Need some advice here.Thanks. Each character is 5ns wide. clkA 10101010 clkb 11110000 Result 1 AA00BB00 Result 2 AAAABBBB I tried the following: both method dont work 1st try task stretch ( input [3:0] value_A , input [3:0] value_B ); @(posedge clkB ) begin module.data = value_A; end @(negedge clkB ) begin module.data = value_B; end endtask : stretch 2nd try task stretch ( input [3:0] value_A , input [3:0] value_B ); @(posedge clkA ) begin module.data = value_A; #10ns; module.data = value_A; end @(posedge clkA ) begin module.data = value_B; #10ns; module.data = value_B; end endtask : stretch Quote Link to comment Share on other sites More sharing options...
calvapete Posted November 3, 2011 Report Share Posted November 3, 2011 Where are you calling this Task? Quote Link to comment Share on other sites More sharing options...
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