Tamilselvan Posted January 7, 2015 Report Share Posted January 7, 2015 Hello all, I'm simulating MOESI protocol for L1 caches in SystemC. I'm getting different results for the same source code when running in SystemC 2.3.0 and SystemC 2.3.1 versions in different machines. Could anyone kindly pass some light on this topic? Machine1: Linux 3.13, Ubuntu 14.04, SystemC 2.3.1, Intel Pentium Dual Core processor. Output - Machine 1: CPU Reads RHit RMiss Writes WHit WMiss Hitrate 0 6 0 6 4 0 4 0.000000 1 34 0 34 22 0 22 0.000000 2 35 0 35 43 0 43 0.000000 3 39 2 37 46 2 44 4.705882 4 36 0 36 55 0 55 0.000000 5 52 0 52 47 0 47 0.000000 6 48 3 45 51 2 49 5.050505 7 42 1 41 55 5 50 6.185567 Total: 292 6 286 323 9 314 15 Avg: 36 0 35 40 1 39 1 2. Main memory access rates Bus had 286 reads and 1 upgrades and 314 readX. A total of 601 accesses. 3. Average time for bus acquisition There were 50 waits for the bus. Average waiting time per access: 0.083195 cycles. 4. There were 1 Cache to Cache transfers 5. Total execution time is 10204 ns, Avg per-mem-access time is 16.978369 ns 6. Probe Read: 5, Probe ReadX: 7 Machine 2: Linux 3.13, Ubuntu 14.04, SystemC 2.3.0, Intel i7 Quad Core processor. Output - Machine 2: CPU Reads RHit RMiss Writes WHit WMiss Hitrate 0 6 0 6 4 0 4 0.000000 1 34 0 34 22 0 22 0.000000 2 35 0 35 43 0 43 0.000000 3 39 2 37 46 2 44 4.705882 4 36 0 36 55 0 55 0.000000 5 52 0 52 47 0 47 0.000000 6 48 3 45 51 2 49 5.050505 7 42 1 41 55 5 50 6.185567 2. Main memory access rates Bus had 286 reads and 0 upgrades and 314 readX. A total of 600 accesses. 3. Average time for bus acquisition There were 51 waits for the bus. Average waiting time per access: 0.085000 cycles. 4. There were 0 Cache to Cache transfers 5. Total execu tion time is 10204 ns, Avg per-mem-access time is 17.006667 ns 6. Probe Read: 1 , Probe ReadX: 0 Does the version 2.3.0 and 2.3.1 are the reason for the inconsistent result? Source code and steps to run the simulation can be found here. Thanks, Tamilselvan Shanmugam. Quote Link to comment Share on other sites More sharing options...
ralph.goergen Posted January 7, 2015 Report Share Posted January 7, 2015 Hi, from SystemC 2.3.0 to SystemC 2.3.1, part of the internal list handling for threads has changed. This can lead to a different execution order of threads runable in the same delta cycle. In general, the execution order of threads in a single delta cycle is undefined in SystemC and models should not rely on this order. When running the same model twice with the same simulator, the order should be the same. But in different simulators the order may differ. Could this be the cause of the difference in your case? If not, could you strip down your example to a minimum (showing the difference but easier to understand)? Greetings Ralph maehne 1 Quote Link to comment Share on other sites More sharing options...
Philipp A Hartmann Posted January 8, 2015 Report Share Posted January 8, 2015 Tamilselvan, I had a quick glance and you're having signals with multiple drivers in your design (at least you're suppressing the related errors). There has been an issue in SystemC 2.3.0, fixed in 2.3.1, which could cause differences in this scenario. Quoting from the 2.3.1 RELEASENOTES: - Handle the case of a suppressed multiple-writer error in sc_signal (and related channels) consistently with SystemC 2.2.0 again. I would suggest to use the proper sc_writer_policy (i.e. SC_MANY_WRITERS) for these signals, if you really can't avoid having multiple SystemC processes driving them. Suppressing errors (or even warnings) is rarely the right thing to do. Greetings from Duisburg, Philipp maehne and David Black 2 Quote Link to comment Share on other sites More sharing options...
Tamilselvan Posted January 25, 2015 Author Report Share Posted January 25, 2015 Hello Philipp A. Hartmann and Ralph Görgen, Thanks for your insight and time. It indeed helped me. Regards, Tamilselvan Shanmugam Quote Link to comment Share on other sites More sharing options...
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