ecpratik

Here is flow to register a sequence with uvm phase along with proper raise and drop objection mechanism inside sequence which is working and running properly : Inside Test’s build phase , registering the sequence with particular UVM phase with help of uvm_config_db : ======================================================================================= virtual function void build_phase(uvm_phase phase); super.build_phase(phase); uvm_config_db#(uvm_object_wrapper)::set(this,"my_tb.my_agent.my_seqr.pre_reset_phase","default_sequence",my_powergood_seq::type_id::get()); uvm_config_db#(uvm_object_wrapper)::set(this,"my_tb.my_agent.my_seqr.reset_phase","default_sequence",my_reset_seq::type_id::get()); uvm_config_db#(uvm_object_wrapper)::set(this,"my_tb.my_agent.my_seqr.configure_phase","default_sequence",my_cfg_seq::type_id::get()); uvm_config_db#(uvm_object_wrapper)::set(this,"my_tb.my_agent.my_seqr.main_phase","default_sequence",my_test_seq::type_id::get()); uvm_config_db#(uvm_object_wrapper)::set(this,"my_tb.my_agent.my_seqr.shutdown_phase","default_sequence",my_flush_seq::type_id::get()); Inside Base Sequence’s pre_body() and post_body() tasks for raise and drop objection mechanism : ======================================================================================= virtual task pre_body(); if (starting_phase!=null) begin `uvm_info(get_type_name(), $sformatf("%s pre_body() raising %s objection", get_sequence_path(), starting_phase.get_name()), UVM_MEDIUM); starting_phase.raise_objection(this); end endtask // Drop the objection in the post_body so the objection is removed when // the root sequence is complete. virtual task post_body(); if (starting_phase!=null) begin `uvm_info(get_type_name(), $sformatf("%s post_body() dropping %s objection", get_sequence_path(), starting_phase.get_name()), UVM_MEDIUM); starting_phase.drop_objection(this); end endtask

Hi jwanger , I tried following sample code to register a sequence in pre_reset phase into build phase of test code and ran with UVM_DEBUG: uvm_config_db #(uvm_object_wrapper)::set(this,"my_tb.my_agent.my_seqr.pre_reset_phase","default_sequence",my_seq::type_id::get()); But it gave me following message : [PHASESEQ] No default phase sequence for phase 'pre_reset' Which means that it did not register the my_seq with pre_reset phase. I cross checked my sequencer path and it is proper. Do we have any working example in which registering sequence to a particular phase is working?

Thanks jadec and uwes for your replies. After lot of try and error , I found easiest way which was to convert OVM test bench to UVM test bench rather to keep test bench partial of OVM and UVM.

Thanks , I have tried your example , but its still not calling the sequence from the test. Following is the sample code which I tried in my test : virtual function void build_phase(uvm_phase phase); super.build_phase(phase); my_tb = my_testbench::type_id::create("my_tb", this); uvm_config_db#(uvm_object_wrapper)::set(this,"my_tb.my_agent.my_seqr.reset_phase","default_sequence",my_seq::type_id::get()); endfunction:build_phase

Hello , I have one sequence x_seq which is associated with x_sequencer. Inside UVM , I think we have facility to register a specific sequence with particular phase. For example : x_seq is reset sequence so it will be associate with reset_phase(). Can anyone explain with example how to register a sequence with a particular phase with the help of uvm_config_db ? Thanks.

Hello , I have one requirement in which I want to convert my tesbench (which instantiate multiple OVCs) from OVM to UVM Before I convert whole OVC into UVC , is it possible to change only top testbench from OVM to UVM without changing sub level components (and OVCs) which are used in that test bench into UVM ? Or we must have to change whole test bench and OVCs into UVM compliant ? Thanks.