Hello All,
The VCS simulator version I am using is v2011.03.mx
I am new to UVM. So, trying to run the simple examples in UVM package. These are the steps performed.
1. I have downloaded the "uvm-1.0p1" package from the website: http://www.accellera.org/activities/vip/
and copied to my folder.
2. My aim is to run the "hello_world" example provided in this package.
3.By default the vcs version I use is 2009.06 and hence I add this to <My_Path>/uvm-1.0p1/examples/Makefile.vcs:
"--v v2011.03.mx" to the vcs command line.
3. Then I go to the folder
<My_Path>/uvm-1.0p1/examples/simple/hello_world and type the command:
make -f Makefile.vcs.
I get compilation error in the file:../../../src/macros/uvm_object_defines.svh,line 692. The entire error message is pasted below.
****************
make -f Makefile.vcs
vcs --v v2011.03.mx -sverilog -timescale=1ns/1ns +acc +vpi +incdir+../../../src ../../../src/uvm.sv ../../../src/dpi/uvm_dpi.cc -CFLAGS -DVCS +incdir+. \
hello_world.sv
cmd: vcs
LM_LICENSE_FILE: 1730@issg-lmgr1:6055@ls-na-west:6055@ls-na-east:6055@ls-csi:11208@smblmgr1:7460@issg-lmgr1
Note: Latest production version of vcs available is v2009.06-2mx
VCS_HOME is set to /auto/edatools/synopsys/vcs/v2011.03.mx
Invoking vcs v2011.03.mx
*** Using c compiler /usr/bin/gcc instead of cc ...
Chronologic VCS
Version E-2011.03 -- Wed Nov 16 15:52:30 2011
Copyright © 1991-2011 by Synopsys Inc.
ALL RIGHTS RESERVED
This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.
Warning-[ACC_CLI_ON] ACC/CLI capabilities enabled
ACC/CLI capabilities have been enabled for the entire design. For faster
performance enable module specific capability in pli.tab file
Parsing design file '../../../src/uvm.sv'
Parsing included file '../../../src/uvm_pkg.sv'.
Parsing included file '../../../src/uvm_macros.svh'.
Parsing included file '../../../src/macros/uvm_version_defines.svh'.
Back to file '../../../src/uvm_macros.svh'.
Parsing included file '../../../src/macros/uvm_message_defines.svh'.
Back to file '../../../src/uvm_macros.svh'.
Parsing included file '../../../src/macros/uvm_phase_defines.svh'.
Back to file '../../../src/uvm_macros.svh'.
Parsing included file '../../../src/macros/uvm_object_defines.svh'.
Error-[sE] Syntax error
Following verilog source has syntax error :
"../../../src/macros/uvm_object_defines.svh", 692: token is 'for'
for(cnt=0; cnt<str__.len(); ++cnt) begin \
^
1 warning
1 error
CPU time: .046 seconds to compile
make-3.79.1-p7: *** [comp] Error 255
****************************
Am I missing something?
Please help me in running the example and compiling any other UVM code using VCS?
Thanks in advance for your help.
