VCS Mixed Simulation VCS VHDL Verilog Mixed language simulation with UVM

[Muhammad Kashif]

This is to state that I am currently working on Mixed-Design (Containing VHDL && Verilog Files) Verification using SVerilog/UVM Testbench.

After building the initial verification environment when I compile the design & TB files together through Makefile script it gives an error that TB top is not able to find the Design instantiation? My design includes a VHDL top with a Verilog file instantiated in it.

I make separate flist files for Verilog VHDL & SVerilog files.

How do I link compiled design (VHDL & Verilog) && UVM testbench files? 

My Makefile commands are mentioned below:

 

vlogan -work work +v2k +incdir+$(UVM_HOME) $(UVM_HOME)/uvm_pkg.sv +libext+.sv -f ./results/vlog_flist.f -ntb_opts uvm-1.2 -full64 -debug_all

vhdlan -work work -f ./results/vhdl_flist.f

vcs -timescale=1ns/1ps -f ./results/build_uvc.f -error=noZONMCM -ntb_opts uvm-1.2 -sverilog -cm line+cond+tgl+fsm -ova_cov -cm_hier config_covg.cfg -cm_name ${TEST} -LDFLAGS -Wl,--no-as-needed -debug_all

cd ./results
cd ./results && mkdir -p $(TEST)_build/SEED_$(SEED)
mv -f csrc* simv* ./results/$(TEST)_build/SEED_$(SEED)/
cd ./results/$(TEST)_build/SEED_$(SEED) && ./simv +UVM_TESTNAME=${TEST} -cm line+cond+tgl+fsm +UVM_TIMEOUT=${TIME_OUT} ->log_${TEST}_build.log

[Peter Grove]

I really think this is a question for your EDA vendor not the standards working group.

Regards

Peter Grove