SCV Constraint

[shaddad]

I am trying to use SCV randomization. I override the next method as shown below. 

We looking at the printed data, I see:

 

DATA 1 DENSITY 0
DATA 1 CAPACITY 2

DATA 2 DENSITY 0
DATA 2 CAPACITY 1

DATA 1 DENSITY 0
DATA 1 CAPACITY 1

DATA 2 DENSITY 0
DATA 2 CAPACITY 3
 

 

This means the next method below (virtual void next())  executed twice instead of once. Why this is happening? 

 

public:
virtual void next() {
 ems_cd__u_ras_config__t_inst->LP5_CAPACITY.disable_randomization();
 scv_constraint_base::next();
 cout << "DATA 1 DENSITY " << ems_cd__u_ras_config__t_inst->LP5_DENSITY.read() << endl; 
 cout << "DATA 1 CAPACITY " << ems_cd__u_ras_config__t_inst->LP5_CAPACITY.read() << endl; 
 ems_cd__u_ras_config__t_inst->LP5_CAPACITY.enable_randomization();
 ems_cd__u_ras_config__t_inst->LP5_DENSITY.disable_randomization();
 scv_constraint_base::next();
 cout << "DATA 2 DENSITY " << ems_cd__u_ras_config__t_inst->LP5_DENSITY.read() << endl; 
 cout << "DATA 2 CAPACITY " << ems_cd__u_ras_config__t_inst->LP5_CAPACITY.read() << endl; 
}

 

 

 

 

[StuartSwan]

You might want to try setting a gdb breakpoint on the next() method and then see what code is calling it. That might help you figure out why it is being called twice..

If you are trying to use SCV to do constrained random stimulus, I'd suggest thinking about using SystemVerilog, perhaps also SV UVM. These are much more mature and widely used. There is an example of using an Verilog/SV testbench on a SC DUT in example 45* in the Matchlib examples kit here:

https://github.com/Stuart-Swan/Matchlib-Examples-Kit-For-Accellera-Synthesis-WG

-Stuart Swan