coderoo

Hi David, Thanks for explaining the issue and providing the fix. Yes, I do need to understand how the simulator handles this. Would you be able to provide any reading references?

I'm testing the instantiation of a SystemC module in a Verilog testbench using VCS. I expect to see a 1-cycle output delay due to flop latency. However, the SystemC module produces the output at the same cycle as the input. The module is a simple counter. The entire code is visible here: https://www.edaplayground.com/x/7reZ Thank you.

Hi, I have a custom class that bundles a few primitive signals: class Bundled { bool block0_en; bool block1_en; sc_int<3> block0_data_in; sc_int<4> block1_data_in; //constructor //operator== //operator= //operator<< //sc_trace }; class Block0; // SC_MODULE class Block1; // SC_MODULE SC_MODULE(Top) { sc_in<Bundled> bundled_in; Block0 block0; Block1 block1; SC_CTOR(Top) : bundled_in("bundled_in") { block0.en(bundled_in.block0_en); // can't do this because block0_en is not a port! ... } }; How do I split this into the individual signals and connect to submodule ports? Is there a convenient/standard way to accomplish this without reading "bundled_in" in an SC_CTHREAD/SC_METHOD, and then writing individual members to sc_signals?