Eyck,
Thank you for your answer. I read the Doulos tutorial, and built a TLM model for a simple RISC-V processor. I still didn't quite see the difference. In systemc, builder uses the functions under tlm_generic_payload class to bind different modules, in systemverilog, builder uses a top module to bind the port of each module together, which for me doesn't seem too different. There is no event-based or conditional trigger between modules in systemverilog. As to the event within the module, systemc does that too (for example, in the first example code from Doulos, they use for loop to generate data, or you may use other conditional statements or fstream object, which are also events).
So where does I get wrong?
Thank you very much!