I have used Modelsim to compare simulation results between a C model encapsulated in SystemC to its VHDL implementation, mostly with a GUI, for hardware verification.
I am trying to see how SystemC can be used for Software validation and/or regression testing using a SystemC testbench that has software modules, SystemC models, and VHDL HW modules when fidelity is needed. I am assuming the open-source SystemC simulator does not support VHDL natively so a VHDL simulator would be needed like modelsim.
What is the best way to use the SystemC open source simulation to make calls to a VHDL simulator like modelsim while reducing the license usage of modelsim?
Can you share your experience and lessons learned regarding mixed language sims?
SystemC and VHDL co-simulation
in SystemC Language
Posted
I have used Modelsim to compare simulation results between a C model encapsulated in SystemC to its VHDL implementation, mostly with a GUI, for hardware verification.
I am trying to see how SystemC can be used for Software validation and/or regression testing using a SystemC testbench that has software modules, SystemC models, and VHDL HW modules when fidelity is needed. I am assuming the open-source SystemC simulator does not support VHDL natively so a VHDL simulator would be needed like modelsim.
What is the best way to use the SystemC open source simulation to make calls to a VHDL simulator like modelsim while reducing the license usage of modelsim?
Can you share your experience and lessons learned regarding mixed language sims?
Thanks
Paul