The Javadoc format for documenting API is well established in the software world, so why not use it for SystemVerilog? It is a pretty simple format and it allows quick access to the API spec, especially when you need something fast.
It doesn't supplement user guides, but it is lightweight and easily browsable. It starts from the assumption the underlying code is well commented. Which seems to be true for the UVM lib.
Needless to say, if you use an IDE (like DVT - www.dvteclipse.com), the API spec is presented inline with the code, so you don't have to open/switch to the API docs while editing.
Still, it is good to have the API at hand, so here it is.