Events
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3
PM
09 June 2015 03:30 PM
Tuesday, June 9 2015
7:30am - 9:00am
Moscone Center, Room 220
Topic: Design and Verification Standards in the Era of IoT
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The era of Internet of Things (IoT) will usher increased use of communication and other protocols for rapid development and interconnect of new devices. These projects will be run on shrinking timelines with more globalized teams, increasing the need for design and verification standards. I2C, MIPI, WiFi and other protocols are already implemented using SystemC, SystemVerilog, UPF, UVM and other standards originated by Accellera and globalized in the IEEE. By working more closely together, the protocol working groups and the design and verification working groups can provide key technology to accelerate development in the era of IoT.
The Accellera breakfast panel brings together senior technologists from the IoT community to discuss the current status and future needs for standards cooperation. We welcome you to join this lively discussion and get your creative minds running before you head into your IoT, automotive, and other sessions at DAC 2015.
Moderator: John Blyler, Editorial Director, Embedded IoT Systems, Portland, OR
Panelists will be announced soon. This event is free to all DAC attendees. Registration is required.
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9
PM
09 June 2015 09:15 PM
Tuesday, June 9 2015
1:15pm - 4:30pm
Moscone Center, Room 206
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Low power remains a hot topic for designers, verification engineers, IP developers and tool providers. In particular, interoperability among tools and IP remains a big concern for the engineers dealing with low power issues. In the past decade, standards have played an important role in building design and verification environment that address interoperability issues. Collectively, as the industry learns how to solve current issues, it uncovers that there are more issues to solve at system level in order to keep up with the growing complexity of designs and processes. Besides agreeing on the definition of system level, creation of power models and their suitability at different levels of abstraction for appropriate analysis remains a challenge.
With this in mind, a System Level Low Power workshop will be held at the 52nd Design Automation Conference (DAC). The workshop is co-organized and sponsored by the IEEE Design Automation Standards Committee (DASC), Si2 and Accellera Systems Initiative.
This workshop is free to all DAC attendees. Registration is required.
Agenda now available >
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