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[UVM Connect] How to connect tlm_analysis_port from SV to SC?

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Hi UVM connect export,

I hope to use tlm_analysis_port in direction SV report to SC (I could only find the other direction in uvmc example) so I try to write my own as following.

By printing some message I found the analysis port in SV side has been written, however the SC side write did not be invoked, could some one give some hint to the problem or how to debug it has been connected correctly? (I am new to SC so there could be some stupid mistake, please forgive me if any) thanks!


class my_subscriber : public sc_module, public tlm_analysis_if <my_pkt> {

virtual void write (const my_pkt &pt) {




int sc_main (int argc, char** argv[]) {

my_subscriber sub("sub");

// uvm_connect(sub, "my_ap");

// I modified previous line to following 2 lines

// because ambiguous call due to multiple inheritance

uvmc_analysis_port<my_pkt> port (sub.name(), "my_ap");



return 0;



uvmc_tlm1 #(my_pkt)::connect(uvm_ap, "my_ap");

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