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How to correlate sequence item property with reg_field


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Hi:

I am trying to incorporate register model into our test environment, but not even sure if I am on the right path.

Let's say I have a sequence item for data transaction with a property, xfer_size, which corresponds to a control register field.

In old days, this sequence item would be passed down to individual bus drivers and the drivers would find the address of those properties (forexample, xfer_size => address 32'h00a0, field mask 32'h00ffff) and carry out the register access.

Now after we create register models, the xfer_size corresponds to "ctlr.mod1.ctl.xfer_size". What is the typical way for bus driver to use this register model to access it?

I am thinking the driver would have to somehow translate req.xfer_size to "ctlr.mod1.ctl.xfer_size", then do reg_field.write(), with the help of an adapter, etc. But it seems quite involved.

Am I on the right path? If so, how should the translation be done?

Thanks.

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Hi:

I can see that register layer model is very helpful in testing registers.

But I am not sure how to use it in other functional tests that require lots of control register read/write to generate/control the transactions.

Has anyone done this in real projects? if so, do you have to re-write your existing sequences?

Thanks.

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  • 4 weeks later...

Phil,

No, This is not the purpose of translation. The translation is always for the interface serving the registers in a DUT. Hence a simple register sequence item is converted to a bus item that could be AHB/WB or any proprietary bus for register read/write. Therefore its a reusable code for most of your DUTs having similar register interfaces.

What you intend to do is percolate the register writes to your bus drivers which make use of the register values. This is a specific implementation that you would need to sort out inside testcases which would run the 2 sequences independently.

A way which we use commonly for this is :

1) Use configure/post_reset/pre_main etc phase to run a generic register sequence. i.e. Randomize the register model and write the entire map to DUT based on certain constraints.

2) In other phase occurring after the above , use the already configured regmodel property inside your driver and perform the usual transactions. The sequence item thus would be independent of the property and would be taken care by the driver instead Or as in your case inside the testcase in a different phase use `uvm_do_with and use inline constraint e.g. `uvm_do_with(req, {req.xfer_size == ctrl.mod1.ctl.xfer_size.get();})

Hope it helps!

Thanks,

Mehul

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