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xiangben

How to use parameterized interface in UVM?

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Hi,

I met some problem when I use parameterized interface in UVM 1.1. I don't know where I made the mistake.

It reported that "UVM_FATAL @ 0.00ns:uvm_test_top.env.ig_il.drv [NOIVF] virtual interface must be set for: uvm_test_top.env.eg_il.drv.if"

If I changed .EBB_SIZE(5),.DATA_SIZE(32) to the default .EBB_SIZE(4),.DATA_SIZE(16), eveything is OK.

Could any help to point out where's wrong? Thanks a lot!

Following is my code:

/////////////////////////////////////////////////////////////////////////////////////////////////////////////////

// Interface definition in il_if.sv

interface il_if #(EBB_SIZE=4, DATA_SIZE=16) (input logic clock);

/////////////////////////////////////////////////////////////////////////////////////////////////////////////////

//interface instantiation in il_tb.sv

il_if #(.EBB_SIZE(5),.DATA_SIZE(32)) drv_if(core_clk);

/////////////////////////////////////////////////////////////////////////////////////////////////////////////////

//Virtual interface assignment in il_top.sv

initial begin

uvm_config_db#(virtual il_if #(.EBB_SIZE(5),.DATA_SIZE(32)))::set(uvm_root::get(),"*drv","vif",il_tb.drv_if);

......

end

/////////////////////////////////////////////////////////////////////////////////////////////////////////////////

//Interface get in il_driver.sv

class il_driver extends uvm_driver #(il_pkt);

protected virtual il_if #(.EBB_SIZE(5),.DATA_SIZE(32)) vif;

......

function void build phase(uvm_phase phase);

super.build_phase(phase);

if(!uvm_config_db #(virtual il_if #(.EBB_SIZE(5), .DATA_SIZE(32)))::get(this,"","vif",vif))

`uvm_fatal("NOVIF",{"virtual interface must be set for:",get_full_name(),".vif"})

endfunction: build_phase

endclass : il_driver

/////////////////////////////////////////////////////////////////////////////////////////////////////////////////

//Create driver in il_agent.sv

class il_agent extends uvm_agent;

il_driver drv;

.....

function void build_phase(uvm_phase phase);

super.build_phase(phase);

drv = il_driver::type_id::create("drv",this);

...

endfunction

endclass: il_agent

Best Regards

Benben

Edited by xiangben

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how do you create create your driver?

Hi uwes,

class il_agent extends uvm_agent;

il_driver drv;

.....

function void build_phase(uvm_phase phase);

super.build_phase(phase);

drv = il_driver::type_id::create("drv",this);

...

endfunction

endclass: il_agent

class il_driver extends uvm_driver #(il_pkt);

protected virtual il_if#(.EBB_SIZE(5),.DATA_SIZE(32)) vif;

......

function build_phase(uvm_phase phase);

super.build_phase(phase);

if(!uvm_config_db #(virtual il_if #(.EBB_SIZE(5),.DATA_SIZE(32)))::get(this,"","vif",vif))

......

endfunction: build_phase

...

endclass:il_driver

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This is also the question I keep asking and not find good answer yet.

But I found an article from here: http://www.vip-central.org/2012/09/parameterized-interfaces-and-reusable-vip-part-3/

I thin it is good. But still a little bit complicated for me.

Hope better solution for this.

Hi enchanter,

Thanks for providing such a good article. I will try it.

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Parameters used for sizing interfaces are like viruses! They propagate to every variable and environment that must use them.

Much better to rely on Verilog's automatic resizing and be done with it. That way, you can write width-generic code.

http://www.vmmcentral.org/vmartialarts/2008/07/size-does-matter/

Hi janick,

Does the "resizing" you mentioned is to declare a maximum size of interface we may use and then assign the interface varibles to a smaller size of interface?

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Hi Benben,

you could try making your interface polymorphic. I found that a very elegant way for the parameterized interface to not behave like a virus, as Janick said. (And he is right.)

Cheers

Gunther

Edited by Gunther

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Hi Benben,

you could try making your interface polymorphic. I found that a very elegant way for the parameterized interface to not behave like a virus, as Janick said. (And he is right.)

Cheers

Gunther

You can find the recipe here: http://verificationhorizons.verificationacademy.com/volume-7_issue-3/articles/stream/polymorphic-interfaces-an-alternative-for-systemverilog-interfaces_vh-v7-i3.pdf

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