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[Bug UVM1.2] uvm_reg does not allow overlapping RO+WO fields


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It is somewhat common to have a register definition be "overloaded" such that there are fields that overlap in the same bit-locations with opposing access policies. For example:

EXAMPLE_REG
    [31:0] STATUS_BITS (RO)
    [7:0]  CONTROL_BITS (WO)

The above example results in the following UVM_ERROR messages stemming from the uvm_reg::add_field() method:

UVM_ERROR verilog_src/uvm-1.2/src/reg/uvm_reg.svh(1243) @ 0 ns: reporter [RegModel] Fields use more bits (40) than available in register "EXAMPLE_REG" (32)
UVM_ERROR verilog_src/uvm-1.2/src/reg/uvm_reg.svh(1252) @ 0 ns: reporter [RegModel] Field STATUS_BITS overlaps field CONTROL_BITS in register "EXAMPLE_REG"

Describing such a structure is valid in IP-XACT (Annex B, SCR 7.2) as well as SystemRDL (Clause 10.1-d). Both inputs are commonly used to generate UVM so it seems an oversight in the UVM implementation to flag this as an error and not consider access policy when validating for overlaps. This type of register overloading structure has been encountered in several 3rd party IPs from various vendors, so it is not particularly obscure.

Interestingly, UVM does allow two registers to share the same address, provided they do not have conflicting access policies. This suggests that the precedent for allowing this structure exists, however the concept was not extended to fields.

Workaround is to have UVM register model code generators detect this condition and automatically split EXAMPLE_REG into two registers - one that is RO and another that is WO. This is workable but not ideal since it requires mangling register path names that otherwise deviate from documentation. With this workaround it is not possible to describe more complex registers that also contain non-conflicting RW fields. For example:

EXAMPLE_REG
    [31:8] OTHER_BITS (RW)
    [7:0]  STATUS_BITS (RO)
    [7:0]  CONTROL_BITS (WO)

 

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