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force and release in systemC


shaddad

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I need to verify a read-only register. I want to force the input of the register to some value and then make sure I can read it thru the front door. In System-Verilog/Verilog, there exists a force release that can be used to force any signal to a particular value. How can I achieve the force release in systemC? Pls help! 

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