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Why simulation complete time is 0 ?


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Hi,

I'am UVM starter and I did download UVM example on the website (http://www.testbench.in/UT_02_UVM_TESTBENCH.html)

(http://www.testbench.in/uvm_phases.tar)

I did not change example except 2 parts below

1. in the top.vs

`include "uvm.svh" -> `include "uvm.sv"

2. in the Makefile

irun ${UVM_FLAGS} +incdir+. ${FILES} +UVM_TESTNAME=test1

->

irun -uvmhome $(UVM_HOME) ${UVM_FLAGS} +incdir+. ${FILES} +UVM_TESTNAME=test1

After $> Make ius

the simulation time is 0 like thie

Simulation complete via $finish(1) at time 0 FS + 186

/net/hw3/work/sclee/my_work/UVM/uvm-1.1a/src/base/uvm_root.svh:408 $finish;

Could yo explain why simulation complete time is 0 ?

Thanks in advance,

Skan, Lee

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hi,

a minor side comment:

1. get rid of ANY "include something of uvm" and replace this with "import uvm_pkg::*;"

2. add "`include uvm_macros.svh" as necessary

3. either add the uvm_pkg.sv file to your list of files to compile OR in the case of ius have irun take care of the compilation using the -uvmhome switch

1-3 will most likely not solve your issue BUT it prevents you from other errors down the road

/uwe

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When you see something like this.

1.Your objections are not being raised or dropped properly.

2. This is usually hidden in the sequence base class (that you create) pre-body and post-body.

I'd have to look at the example and see where this is. If it's a simple test with no sequences, it can be placed in the run_phase of the test.

In fact if you want to debug this in the run_phase do as the first item:

phase.raise_objection

phase.drop_objection as the last item.

Since i don't have the example -- I don't know what they are doing. You might want to run a few of the example provided with the uvm1.1a release.

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This is really old code.

1. All the phases should be declared xxx_phase (uvm_phase phase)

2. global_stop_request is no longer used

The test is working though sort of. You just are running through all the phases and printing messages. Once run_test is called, the phasing system kicks off. All the phases except run_phase take 0 time. The run_phase in this example doesn't raise or drop objections, so your wait of #1000 doesn't happen.

change your run to run_phase like this :

virtual task run_phase (uvm_phase phase);
        phase.raise_objection(this);
        #1000;
        phase.drop_objection(this);
    endtask : run

This is what the reporter says:

** Report counts by severity

UVM_INFO : 58

UVM_WARNING : 0

UVM_ERROR : 0

UVM_FATAL : 0

** Report counts by id

[RNTST] 1

[uvm_test_top] 1

[uvm_test_top.t_env] 8

[uvm_test_top.t_env.ag1] 8

[uvm_test_top.t_env.ag1.drv] 8

[uvm_test_top.t_env.ag1.mon] 8

[uvm_test_top.t_env.ag2] 8

[uvm_test_top.t_env.ag2.drv] 8

[uvm_test_top.t_env.ag2.mon] 8

Old Message:

Simulation complete via $finish(1) at time 0 FS + 186

New Message:

Simulation complete via $finish(1) at time 1 US + 44

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  • 4 weeks later...
Guest joseph.steve

Thanks for the sharing first actually.Actually i think that biased time are skipped so that is why the simulation time is always minimum.

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  • 1 year later...

Thanks lisakb1963

 

Here's the log

 

# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(215) @ 0: reporter [Questa UVM] QUESTA_UVM-1.2
# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(217) @ 0: reporter [Questa UVM]  questa_uvm::init(+struct)
# UVM_INFO @ 0: reporter [RNTST] Running test test1...
# UVM_INFO @ 0: uvm_test_top.t_env [uvm_test_top.t_env] Build
# UVM_INFO @ 0: uvm_test_top.t_env.ag1 [uvm_test_top.t_env.ag1] Build
# UVM_INFO @ 0: uvm_test_top.t_env.ag1.drv [uvm_test_top.t_env.ag1.drv] Build
# UVM_INFO @ 0: uvm_test_top.t_env.ag1.mon [uvm_test_top.t_env.ag1.mon] Build
# UVM_INFO @ 0: uvm_test_top.t_env.ag2 [uvm_test_top.t_env.ag2] Build
# UVM_INFO @ 0: uvm_test_top.t_env.ag2.drv [uvm_test_top.t_env.ag2.drv] Build
# UVM_INFO @ 0: uvm_test_top.t_env.ag2.mon [uvm_test_top.t_env.ag2.mon] Build
# UVM_INFO @ 0: uvm_test_top.t_env.ag1.drv [uvm_test_top.t_env.ag1.drv] Connect
# UVM_INFO @ 0: uvm_test_top.t_env.ag1.mon [uvm_test_top.t_env.ag1.mon] Connect
# UVM_INFO @ 0: uvm_test_top.t_env.ag1 [uvm_test_top.t_env.ag1] Connect
# UVM_INFO @ 0: uvm_test_top.t_env.ag2.drv [uvm_test_top.t_env.ag2.drv] Connect
# UVM_INFO @ 0: uvm_test_top.t_env.ag2.mon [uvm_test_top.t_env.ag2.mon] Connect
# UVM_INFO @ 0: uvm_test_top.t_env.ag2 [uvm_test_top.t_env.ag2] Connect
# UVM_INFO @ 0: uvm_test_top.t_env [uvm_test_top.t_env] Connect
# UVM_INFO @ 0: uvm_test_top.t_env.ag1.drv [uvm_test_top.t_env.ag1.drv] End_of_elaboration
# UVM_INFO @ 0: uvm_test_top.t_env.ag1.mon [uvm_test_top.t_env.ag1.mon] End_of_elaboration
# UVM_INFO @ 0: uvm_test_top.t_env.ag1 [uvm_test_top.t_env.ag1] End_of_elaboration
# UVM_INFO @ 0: uvm_test_top.t_env.ag2.drv [uvm_test_top.t_env.ag2.drv] End_of_elaboration
# UVM_INFO @ 0: uvm_test_top.t_env.ag2.mon [uvm_test_top.t_env.ag2.mon] End_of_elaboration
# UVM_INFO @ 0: uvm_test_top.t_env.ag2 [uvm_test_top.t_env.ag2] End_of_elaboration
# UVM_INFO @ 0: uvm_test_top.t_env [uvm_test_top.t_env] End_of_elaboration
# UVM_INFO @ 0: uvm_test_top [uvm_test_top] End_of_elaboration
# ----------------------------------------------------------
# Name                   Type                    Size  Value
# ----------------------------------------------------------
# uvm_test_top           test1                   -     @501 
#   t_env                env                     -     @509 
#     ag1                agent                   -     @519 
#       drv              driver                  -     @543 
#         rsp_port       uvm_analysis_port       -     @560 
#         sqr_pull_port  uvm_seq_item_pull_port  -     @551 
#       mon              monitor                 -     @535 
#     ag2                agent                   -     @527 
#       drv              driver                  -     @580 
#         rsp_port       uvm_analysis_port       -     @597 
#         sqr_pull_port  uvm_seq_item_pull_port  -     @588 
#       mon              monitor                 -     @572 
# ----------------------------------------------------------
# UVM_INFO @ 0: uvm_test_top.t_env.ag1.drv [uvm_test_top.t_env.ag1.drv] Start_of_simulation
# UVM_INFO @ 0: uvm_test_top.t_env.ag1.mon [uvm_test_top.t_env.ag1.mon] Start_of_simulation
# UVM_INFO @ 0: uvm_test_top.t_env.ag1 [uvm_test_top.t_env.ag1] Start_of_simulation
# UVM_INFO @ 0: uvm_test_top.t_env.ag2.drv [uvm_test_top.t_env.ag2.drv] Start_of_simulation
# UVM_INFO @ 0: uvm_test_top.t_env.ag2.mon [uvm_test_top.t_env.ag2.mon] Start_of_simulation
# UVM_INFO @ 0: uvm_test_top.t_env.ag2 [uvm_test_top.t_env.ag2] Start_of_simulation
# UVM_INFO @ 0: uvm_test_top.t_env [uvm_test_top.t_env] Start_of_simulation
# UVM_INFO @ 0: uvm_test_top.t_env [uvm_test_top.t_env] Run
# UVM_INFO @ 0: uvm_test_top.t_env.ag2 [uvm_test_top.t_env.ag2] Run
# UVM_INFO @ 0: uvm_test_top.t_env.ag2.mon [uvm_test_top.t_env.ag2.mon] Run
# UVM_INFO @ 0: uvm_test_top.t_env.ag2.drv [uvm_test_top.t_env.ag2.drv] Run
# UVM_INFO @ 0: uvm_test_top.t_env.ag1 [uvm_test_top.t_env.ag1] Run
# UVM_INFO @ 0: uvm_test_top.t_env.ag1.mon [uvm_test_top.t_env.ag1.mon] Run
# UVM_INFO @ 0: uvm_test_top.t_env.ag1.drv [uvm_test_top.t_env.ag1.drv] Run
# UVM_INFO verilog_src/uvm-1.1a/src/base/uvm_objection.svh(1120) @ 1000: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase
# UVM_INFO @ 1000: uvm_test_top.t_env.ag1.drv [uvm_test_top.t_env.ag1.drv] Extract
# UVM_INFO @ 1000: uvm_test_top.t_env.ag1.mon [uvm_test_top.t_env.ag1.mon] Extract
# UVM_INFO @ 1000: uvm_test_top.t_env.ag1 [uvm_test_top.t_env.ag1] Extract
# UVM_INFO @ 1000: uvm_test_top.t_env.ag2.drv [uvm_test_top.t_env.ag2.drv] Extract
# UVM_INFO @ 1000: uvm_test_top.t_env.ag2.mon [uvm_test_top.t_env.ag2.mon] Extract
# UVM_INFO @ 1000: uvm_test_top.t_env.ag2 [uvm_test_top.t_env.ag2] Extract
# UVM_INFO @ 1000: uvm_test_top.t_env [uvm_test_top.t_env] Extract
# UVM_INFO @ 1000: uvm_test_top.t_env.ag1.drv [uvm_test_top.t_env.ag1.drv] Check
# UVM_INFO @ 1000: uvm_test_top.t_env.ag1.mon [uvm_test_top.t_env.ag1.mon] Check
# UVM_INFO @ 1000: uvm_test_top.t_env.ag1 [uvm_test_top.t_env.ag1] Check
# UVM_INFO @ 1000: uvm_test_top.t_env.ag2.drv [uvm_test_top.t_env.ag2.drv] Check
# UVM_INFO @ 1000: uvm_test_top.t_env.ag2.mon [uvm_test_top.t_env.ag2.mon] Check
# UVM_INFO @ 1000: uvm_test_top.t_env.ag2 [uvm_test_top.t_env.ag2] Check
# UVM_INFO @ 1000: uvm_test_top.t_env [uvm_test_top.t_env] Check
# UVM_INFO @ 1000: uvm_test_top.t_env.ag1.drv [uvm_test_top.t_env.ag1.drv] Report
# UVM_INFO @ 1000: uvm_test_top.t_env.ag1.mon [uvm_test_top.t_env.ag1.mon] Report
# UVM_INFO @ 1000: uvm_test_top.t_env.ag1 [uvm_test_top.t_env.ag1] Report
# UVM_INFO @ 1000: uvm_test_top.t_env.ag2.drv [uvm_test_top.t_env.ag2.drv] Report
# UVM_INFO @ 1000: uvm_test_top.t_env.ag2.mon [uvm_test_top.t_env.ag2.mon] Report
# UVM_INFO @ 1000: uvm_test_top.t_env.ag2 [uvm_test_top.t_env.ag2] Report
# UVM_INFO @ 1000: uvm_test_top.t_env [uvm_test_top.t_env] Report
# 
# --- UVM Report Summary ---
# 
# ** Report counts by severity
# UVM_INFO :   61
# UVM_WARNING :    0
# UVM_ERROR :    0
# UVM_FATAL :    0
# ** Report counts by id
# [Questa UVM]     2
# [RNTST]     1
# [TEST_DONE]     1
# [uvm_test_top]     1
# [uvm_test_top.t_env]     8
# [uvm_test_top.t_env.ag1]     8
# [uvm_test_top.t_env.ag1.drv]     8
# [uvm_test_top.t_env.ag1.mon]     8
# [uvm_test_top.t_env.ag2]     8
# [uvm_test_top.t_env.ag2.drv]     8
# [uvm_test_top.t_env.ag2.mon]     8
# ** Note: $finish    : /usr/mentor/questa_sim/linux_x86_64/../verilog_src/uvm-1.1a/src/base/uvm_root.svh(408)
#    Time: 1 us  Iteration: 54  Instance: /top
 
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