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Is it possible to perform AND operation on two ports and connect them while instatiating?


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The code looks something like this:

module1.h

template <int size> class module1 : public sc_module {

public:

sc_in<bool> WRITE_EN;

sc_in<bool> clk;

sc_in<bool> reset;

//NOTE: NO WRITE_ADDR PORT IN THIS MODULE

 

SC_HAS_PROCESS(module1);

module1(sc_module_name name) : sc_module(name)

{

SC_METHOD(prc_mod1);

sensitive << clk << reset;

}

 

void prc_mod1 ()

{

...

..

}

};

 

module2.h

 

#include "module1.h"

template<unsigned N, unsigned M> class module2 : public sc_module

{

public:

sc_in<sc_biguint<2*M> > WRITE_ADDR;

sc_in<bool> WRITE_EN;

sc_biguint<2*M> write_addr_var;

bool write_en_var;

sc_vector<module1<N>> mod1;

 

SC_HAS_PROCESS(module2);

module2(sc_module_name name); sc_module(name), mod1("mod1", M)

{

SC_METHOD(prc_mod2);

write_addr_var = WRITE_ADDR;

write_en_var = WRITE_EN;

for(i=0; i< M; ++i)

{

auto& m1 = mod1[i];

m1.WRITE_EN(write_en_var && write_addr_var[i]) 

//Other ports connections

...

...

}

}

void prc_mod2()

{

...

...

}

};

 

I have two questions here:

1) Is it possible to perform this operation while connecting?

2) I took write_addr_var and write_en_var dummy variable to store the contents of the respective ports to perform && and bit select operation because these operations cannot be performed on ports. But at this point the actual ports are not connected yet and obviously gives "port is not bound" error. Also, there is no WRITE_ADDR port in module1 and it cant be connected.

Please suggest some ways to deal with this problem.

Thanks

 

 

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To answer your first question: no, it is not possible. And they way you try to implement is leads to the problem in your second question. The &&  operator is not a structural operation (like in verilog where you instantiate an and gate). The operator is a function. So you need to move you logic and assigment into the method. The constructor just connects everything togehter. So module2 should look like

#include "module1.h"
template<unsigned N, unsigned M> 
class module2 : public sc_module {
public:
  sc_in<sc_biguint<2*M> > WRITE_ADDR;
  sc_in<bool> WRITE_EN;
  sc_vector<module1<N>> mod1;
  sc_vector<sc_signal<bool> > M1_WRITE_EN;

  SC_HAS_PROCESS(module2);
  module2(sc_module_name name); sc_module(name), mod1("mod1", M){
    SC_METHOD(prc_mod2);
    SC_METHOD(assign_addr);
    sensitive << WRITE_ADDR << WRITE_EN;
    for(i=0; i< M; ++i){
      mod1[i].WRITE_EN(M1_WRITE_EN[i]);
    }
    //Other ports connections
  }

  void assign_addr(){
    for(i=0; i< M; ++i){
      (M1_WRITE_EN[i] = write_en_var.read() && WRITE_ADDR.read()[i])  
    }
  }
  
  void prc_mod2() {
	...
	...
 }
};

 

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