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That surprises me a bit, I assumed that there would be no such "hard" requirements on virtual registers, and that that would be the motivation to have the feature to begin with.

Looking at my problem from the other direction then, if I have several addressblocks inside a memorymap, the databus and the registers being 32 bit. Then there is a special addressblock that contains some wider (e.g. 128 bit, or even more) datastructures. Those are also updated over the 32 bit bus, the updates are made safe somehow, e.g. through buffered writes, or some more global synchronisation (like disable the block, update the addressblock, then enable again).
I would have thought that would be a task for the virtual registers, but if not, how would I model such data structures in IP-XACT?

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Hi Mats,

As you say, you can add a special address block with a width of 128 (or more). The width indicates the maximum number of bits that can be accessed in a single transaction. This address block can contain registers with a size equal to the width or smaller.

Best regards,
Erwin

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