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Hierarchical names in constant expression


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If an IP should be designed with a parameterized interface and additional ports, which should use the same parameter, then this cannot be directly handled in SystemVerilog.

So, obviously, you cannot write something like

interface bus #(N = 8) ();
  logic [N-1:0] adr;
   
  modport send (
    output adr);

endinterface

module m
  (bus.send intf0,
   input adr_pure1 [intf0.N-1:0]);
endmodule

So, the parameter has to provided twice. Unfortunately, it is even not possible to do a check at elaboration time that the values are identical.

interface bus #(N = 8) ();
  logic [N-1:0] adr;
   
  modport send (
    output adr);

endinterface

module m
  #(M = 8)
   (bus.send intf0,
    input adr_pure1 [M-1:0]);

   if (M != intf0.N) $error("unequal parameters");
endmodule

Hierarchical names cannot be used in constant expression. Is there a good reason for this limitation?

Best regards,

  Thomas

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I think defparam is partly to blame here. Before introducing the inline parameter override syntax using #(param1,...) in Verilog-2001, it was very difficult to predict when a parameter had received its final elaborated value relative the the module referencing it. Adding generate constructs makes that process even harder when you start allowing hierarchical references to parameters outside you instance, before the instance hierarchy has been fully elaborated. So the "no hierarchical names" rule is a broad hammer.

In your particular example, you can get around this rule by using typedef instead of parameter references. SystemVerilog allows referencing a type from an interface port because there is a strict relationship between the interface instance and the port it is connected to. 

 

interface bus #(N = 8) ();
  typedef logic [N-1:0] adr_t;
  logic [N-1:0] adr;
   
endinterface

module m
  #(M = 8)
  (bus intf0,
    input [M-1:0] adr_pure1 );
     typedef intf0.adr_t adr_t; // bring interface type into local scope

  if (M != $bits(adr_t)) $error("unequal parameters");
endmodule

module top;
  
  
  bus b();
  m       m1(b,'0); // no error
  m #(10) m2(b,'0); // error
  
endmodule

 

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