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AHB RAL is not updating the correct value


How to make the adapter,s bus2reg function sample the data at correct timestamp  

  1. 1. How to make the adapter,s bus2reg function sample the data at correct timestamp

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I am trying to create and RAL for AHB bus. My adapter is not able to read the data correctly.

My env uses a synopsis AHB VIP.VIP is configured to 32bit address and data.

Write is working with this adapter. Read is delayed by one clock cycle which is making read data from adapter as 0’s always.

Here is the sim.log displays from adapter:

@ 78400823500: reporter [RAL ADAPTER] reg2bus rw.DATA = 00, rw.ADDRESS = 20c

@ 78400823500: reporter [RAL ADAPTER] reg2bus tr.DATA = 00, tr.ADDRESS = 20c

@78400823500 address is on reg2bus

@ 78412835500: reporter [RAL ADAPTER] bus2reg rw.DATA = 00, rw.ADDRESS = 20c

@ 78412835500: reporter [RAL ADAPTER] bus2reg tr.DATA = 00, tr.ADDRESS = 20c

In waveform @78409832500 we can see data on hrdata lines, but bus2reg displays shows timestamps @ 78412835500: by this timestamp data is zero on hrdata.

Can anyone tell me What should be made to adapter so that it read data at correct timestamp.

I have attached the snapshot of read transaction at @ 78400823500,@78409832500,@ 78412835500

Here is the adapter code which I have implemented.

class reg_adapter extends uvm_reg_adapter;

`uvm_object_utils(reg_adapter)

function new (string name = "reg_adapter");

super.new(name);

provides_responses = 1;

endfunction : new

virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw);

pcie_dw_vip_ahb_master_transaction tr;

tr = pcie_dw_vip_ahb_master_transaction::type_id::create("tr");

tr.m_enXactType = (rw.kind == UVM_READ) ? pcie_dw_vip_ahb_master_transaction::READ : pcie_dw_vip_ahb_master_transaction::WRITE;

tr.m_enXferSize = pcie_dw_vip_ahb_master_transaction::XFER_SIZE_32BIT;

tr.m_bvAddress = rw.addr;

tr.m_nNumBytes = 4;

tr.m_bvvData = new[4];

tr.m_bvvData[0] = rw.data[7:0];

tr.m_bvvData[1] = rw.data[15:8];

tr.m_bvvData[2] = rw.data[23:16];

tr.m_bvvData[3] = rw.data[31:24];

`uvm_info("RAL ADAPTER",$sformatf("reg2bus rw.DATA = %2h, rw.ADDRESS = %2h",rw.data,rw.addr),UVM_LOW);

`uvm_info("RAL ADAPTER",$sformatf("reg2bus tr.DATA = %2h, tr.ADDRESS = %2h",{tr.m_bvvData[0],tr.m_bvvData[1],tr.m_bvvData[2],tr.m_bvvData[3]},tr.m_bvAddress),UVM_LOW);

return tr;

endfunction

virtual function void bus2reg(uvm_sequence_item bus_item, ref uvm_reg_bus_op rw);

pcie_dw_vip_ahb_master_transaction tr;

if(!$cast(tr,bus_item))begin

`uvm_fatal("NOT_HOST_REG_TYPE","bus_item is not correct type");

end

rw.kind = (tr.m_enXactType == pcie_dw_vip_ahb_master_transaction::READ) ? UVM_READ : UVM_WRITE;

tr.m_enXferSize = pcie_dw_vip_ahb_master_transaction::XFER_SIZE_32BIT;

rw.addr = tr.m_bvAddress;

tr.m_nNumBytes = 4;

tr.m_bvvData = new[4];

rw.data[7:0] = tr.m_bvvData[0];

rw.data[15:8] = tr.m_bvvData[1];

rw.data[23:16] = tr.m_bvvData[2];

rw.data[31:24] = tr.m_bvvData[3];

rw.status = UVM_IS_OK;

`uvm_info("RAL ADAPTER",$sformatf("bus2reg rw.DATA = %2h, rw.ADDRESS = %2h",rw.data,rw.addr),UVM_LOW);

`uvm_info("RAL ADAPTER",$sformatf("bus2reg tr.DATA = %2h, tr.ADDRESS = %2h",{tr.m_bvvData[0],tr.m_bvvData[1],tr.m_bvvData[2],tr.m_bvvData[3]},tr.m_bvAddress),UVM_LOW);

endfunction

endclass

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