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Array of SystemVerilog Interface


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I get an error with an array of an interface, when I try to use one single element of the array addressed by an variable index:

interface single_if;
  logic [7:0] data_orig;
  logic [7:0] data_modified;
    modport slave (
      input data_orig,
      output data_modified
    );
    modport master (
      output data_orig,
      input data_modified
    );
endinterface

module bus_bridge
  #(
    in_p = 2
  )
  (
    single_if.master array_if_in [0:in_p-1],
    input logic [$clog2(in_p)-1:0] sel,
    single_if.slave single_if_out
  );

  assign single_if_out.data_modified = array_if_in[sel].data_modified;  // error: sel is not a constant object
endmodule

I've tried two tools and both do not accept sel if it is not constant. Is this a rule of SystemVerilog or just a tool limitation?

I could not find any hint in the LRM that such an indexing is not valid.

 

Best regards,

  Thomas

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It's not legal to dynamically select an instance of a module or interface. Elaboration flattens out all hierarchy. Arrays of instances are not true arrays like a variable. Each element could have different characteristices because of defparam, bind, and port connections.  The BNF does not allow the syntax. 

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