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Verifying SystemC model with Verilog/SV testbench


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Hi,

Is it possible to verify a SystemC model using a verilog based or SystemVerilog based testbench? Is there a way to connect the C-model ports to testbench ports using wires without using TLM ports/sockets?

 

Thanks in advance.

Regards,

Nithin

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  • 2 months later...

Hi,

Thank you David and "basarts"

One follow up question on this. I found that it is possible to use SYSCAN to instantiate C-models in RTL testbench and do VCS simulation. Unfortunately SYSCAN is having some issues with latest version of VCS. I am wondering if there is some way to get rid of SYSCAN and use some other method to run VCS simulation in RTL testbench with C-model instantiation.

Thanks in advance.

Regards,

Nithin

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