salmantanvir 0 Posted December 14, 2020 Report Share Posted December 14, 2020 The uvm_reg::do_predict() method contains an if clause which is true when the status field of the register is set to UVM_IS_OK. However it seems the begin end statements are unintentionally missed which causes the prediction to be done also when the status is UVM_NOT_OK. I would expect prediction to be skipped and it seems from the indentation that this was also intended by the implementer. Another issue related to the incorrect processing of the status field (UVM_NO_OK) in uvm_reg_predictor::write() has been open for quite some time at: 0005449: uvm_reg_predictor ignores status of bus_op - Accellera Mantis (mantishub.io) Would it be possible for someone from the UVM working group to provide an estimate as to when these issues can be resolved. Thanks Quote Link to post Share on other sites
zaidiash 0 Posted January 5 Report Share Posted January 5 Mantis added for the topic: 0007259: uvm_reg::do_predict() "begin end statements are unintentionally missed" - Accellera Mantis (mantishub.io) Quote Link to post Share on other sites
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