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tlm_utils::simple_target_socket<> as static member of a module


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Hi All,

Is it possible to have simple_target_socket as static member of a module ? It needs to defined outside the class, can we define and initialize it in constructor ?

// header

class my_module : public sc_core::sc_module {

 public:
       my_module(sc_module_name name);
       static bool isSockettInitialized_;
       static tlm_utils::simple_target_socket<my_module> socket_;
};

// source file 

//instantiate socket, cannot initialize it, because it is outside sc_module - it would throw and E100 error.         
tlm_utils::simple_target_socket<my_module> my_module::socket_;   
bool my_module::isSockettInitialized_ = false;

my_module::my_module(sc_module_name name)
     : sc_module(name) {

     if (!isSocketInitialized){
         isSocketInitialized = true;
        // would like to initialize socket_, here, but tlm_utils::simple_target_socket<> class disables assignment operator
     }
} 

 

I am unable to find a way to initialize the socket_.

1. If I initialize it outside constructor - I get the error - "Error: (E100) port specified outside of module:"

2. Do not know how to initialize in constructor (as the assignment is disabled) 

Please help.

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Hi David,

Thanks for you time and response. 

1. If I use initializer list of constructor, I would be initializing the socket (a static variable) multiple times. I am looking to design the code in such a way that multiple instances of my_module will all same same socket to send/receive their request.

2. I do not understand uniform initialization syntax. After I declare 

static tlm_utils::simple_target_socket<my_module> socket; 

in the definition of class my_module and define the static variable in my source file as 

tlm_utils::simple_target_socket<my_module> my_module::socket_;   

I tried initializing it (conditionally, in the constructor) as -

socket_ = tlm_utils::simple_target_socket<my_module>("socket")

 But this run into compiler error as, the socket's assignment operator is disabled/not-allowed.

Thanks.

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Using the same socket for multiple modules indicates a fundamental conceptual error in how modules, threads and SystemC work. Multiple issues:

1. Sockets are intended to model hardware communication points, but not actual wires. Modules are intended to model silicon hardware blocks. Silicon cannot be assigned (copied or moved within an implementation). Modules are intended to each have their own sockets/ports and are disallowed specifically from sharing.

2. You can have multiple initiator modules communicate with a single target module using a multi socket. If you expect, initiators to talk to other initiators, think again since that is not the concept of initiators. For a given transaction, each module acts as either an initiator or a target. If you need two-way communication (i.e., modules initiating from each side), then you will need both initiator and target sockets on both modules.

Suggestion: Draw the hardware you are trying to model and supply a diagram for us to consider.

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  • 3 weeks later...

1. Cluster – Is a module, which hosts various compute elements, and multiple arrays of DMEs. In this block diagram two DME-Array – each comprising of 4 DMEs is shown. Cluster is connected to multiple NoCs. Each DME-Array is connected to a NoC based on memory type that the array hosts.

2. DME – Dma and memory element. One DME differs from another in terms of size/banks, security and power characteristics (voltage, and power states) of its memory. There are specific NoC to connect DME-Arrays with specific mem type. There could be multiple NoCs, each connecting common MemType DM arrays. Two such NoCs are shown.

3. DME-Arrays would exchange data with DME-Arrays of another cluster over Noc. We want to model this using convenience sockets.  All Transactions originating or terminating from a DME of an DME-Array, would be arbitrated using simple round robin method, and sent to NoC using simple_initiator_socket shown as green bubble. Tx is received in DME-Array from NoC using simple_target_socket using yellow bubble.

4. We want only a pair of initiator / target socket serving all elements of a DME-Array. We would like to instantiate these sockets inside DME class – but have it as static member of the DME-class. This is prohibited by design of the convenience sockets. For now we have instantiated the sockets in Cluster class which is parent of DME. This clutters Cluster class – as these sockets are not used by Cluster class directly or indirectly. They are there because DME would use/access them via parent pointer.
 

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I don't know where you got that specification, but it looks suspiciously like a university project. Also, whoever is using the word 'static' is not using the word correctly. Nor would or should that approach ever work. The diagram implies a hierarchy of SystemC modules with a cluster module  containing several DME-array modules, which in turn contain DME, DMA and MemType2 modules. These could of course be modeled without the illustrated boundaries, but it would add unnecessary complication. The outermost module (Cluster module) would have one each of an initiator and target TLM-2.0 socket (NOT static). You might choose to have a intervening convenience method to allow the "pointer" design that is requested.

 

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