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VCS 2019.06 strong and weak support


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Does VCS 2019.06 support strong and weak?   (Or is there a VCS switch needed to use LRM 2009+?)
I get the following error with the code below.

Error-[IND] Identifier not declared
testbench.sv, 15
  Identifier 'weak' has not been declared yet. If this error is not expected, 
  please check if you have set `default_nettype to none.
  


Error-[IND] Identifier not declared
testbench.sv, 16
  Identifier 'strong' has not been declared yet. If this error is not 
  expected, please check if you have set `default_nettype to none.

 

Code:

//Weak & Strong seem to not work in VCS 2019.06
module top;
  bit clk;

  initial begin
    #100;
    $finish;
  end

  always
    clk=#5~clk;

  AS_TRUE5        : assert property (@(posedge clk)        (1[*5]) ); //per 2009+ LRM, this should be weak by default, so pass
  AS_TRUE5_WEAK   : assert property (@(posedge clk) weak   (1[*5]) ); //per 2009+ LRM, this should pass
  AS_TRUE5_STRONG : assert property (@(posedge clk) strong (1[*5]) ); //per 2009+ LRM, this should fail **1

      //**1:  Should fail because at end of sim, there will be one or more start cycles, which were not the start of five cycles (because sim ends).  So for those, the seq does not complete
endmodule

 

https://edaplayground.com/x/29PM
 

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Thank you.  I could not (easily, so I gave up) find information about the compiler switches online. 

a) -sv=2009 works and the compiler error disappears

b) The assertion AS_TRUE5_STRONG does not fail, as expected, based on the LRM description of "strong".

IEEE_Std1800-2017 : 16.12.2 Sequence property

Quote

strong(sequence_expr) evaluates to true if, and only if, there is a nonempty match of the sequence_expr.

Aren't the clock cycles of the sequence which do not complete (because the simulation ends) empty matches?

 

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Your code works correctly on three other EDAPlayground simulators. 

Yes, thanks Dave.  (I saw that.  I was trying not to make comparisons between them, lest I violate some benchmarking rule or such.)
(I'll move on to another topic now, as I work to get the rust off of my SystemVerilog skills.)


 

 

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