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VCS run option to use random seed?


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@kurtlin , do you know this by chance?   

I am looking for each VCS simulation 'run' to use a different seed. 

(I'm using EDAPlayground, so don't have access to a set of user guides.)

 

On a related note to compile switches, besides replacing -sverilog with -sv=2009, as you showed in another thread **1, I found this below.  (I suspect that -sv=2009 is a superset of "-assert svaext".  So, I'll probably stick with that.  Thanks again.)

Quote

"You must use the –assert svaext compile-time option to enable the new IEEE Std. 1800-2009 compliant SVA features."

 

Perhaps I might set the seed from within the code, performing a string operation on the output of $system("date")

**1: 

 

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