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Hi,

I know this will sound weird, but I will ask anyway :D

I have recently completed my first ASIC design(Front end and functional verification). Although I used some SystemVerilog constructs like functions and tasks and some other stuff, but really I verified whole digital part without UVM.

My question is: What are the advantages of UVM, and why UVM is needed in the first place, as it seems that tasks and functions can verify any design(it seems only, but I am not so much experienced).

Will learned members shed some light on it?

Thanks in advance and best wishes in fight against Corona

 

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UVM is all about reuse. Reuse has several different aspects:

  1. Reuse of an engineers knowledge -- those experienced with UVM can usually jump onto an existing or new UVM project with very little ramp time. I have seen some verification environments using their own methodology that literally took months for new engineers to come up to speed on. Mind you misuse of UVM can lead to the same conclusion if you don't stay within the standard itself.
  2. Reuse of verification components -- means you can reuse a UVM environment without editing a single line of code provided by that environment. This is huge. It is possible to purchase UVM components that test standard interfaces (e.g., 1G Ethernet) and not have to create the code yourself. It still requires the expertise to plug the component into your environment, but it is relatively easy to do.

UVM also means application of a tried and tested methodology rather than role your own.

Downsides to UVM include:

  1. UVM is fairly complex and to get the most out of it generally requires training
  2. UVM is fairly large as a body of code and has a lot of boilerplate code

Bottom-line: You don't have to use UVM to verify your code, but if your designs are large enough, it seem crazy not to adopt it. You can hire employees and contractors that know how to do leverage UVM and purchase components to shorten your design task. For small/tiny designs, it may not make sense.

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20 hours ago, David Black said:

UVM is all about reuse. Reuse has several different aspects:

  1. Reuse of an engineers knowledge -- those experienced with UVM can usually jump onto an existing or new UVM project with very little ramp time. I have seen some verification environments using their own methodology that literally took months for new engineers to come up to speed on. Mind you misuse of UVM can lead to the same conclusion if you don't stay within the standard itself.
  2. Reuse of verification components -- means you can reuse a UVM environment without editing a single line of code provided by that environment. This is huge. It is possible to purchase UVM components that test standard interfaces (e.g., 1G Ethernet) and not have to create the code yourself. It still requires the expertise to plug the component into your environment, but it is relatively easy to do.

UVM also means application of a tried and tested methodology rather than role your own.

Downsides to UVM include:

  1. UVM is fairly complex and to get the most out of it generally requires training
  2. UVM is fairly large as a body of code and has a lot of boilerplate code

Bottom-line: You don't have to use UVM to verify your code, but if your designs are large enough, it seem crazy not to adopt it. You can hire employees and contractors that know how to do leverage UVM and purchase components to shorten your design task. For small/tiny designs, it may not make sense.

Yes may be, my design was fairly small. Small Sensor ASIC. Thanks for detailed answer sir.

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