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I wish to monitor two signals and wish to determine which of the two changes first and then do some work. 

module tb(
input sel1,
input sel2
);
//Determining which of the two changes first
// if sel1 changed first 
	//do some work
//else
	//do some other work

endmodule

There are two signals sel1 and sel2 and I wish to monitor which of the following changed first and then do some work. Can someone help me in doing the same. 

Thank you.

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module who_changed_first(input a, b, start);
always @(posedge start) begin
  byte changed;
  WATCHERS: fork
    @a changed = "a";
    @b changed = "b";
  join_any
  disable WATCHERS; //< prevent others from overwriting
  case (changed)
    "a": work_1;
    "b": work_2;
  endcase
end

Assumes SystemVerilog. If Verilog you will need to add .

See https://edaplayground.com/x/2NXz for example code.

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