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Hiiiii.........I wrote simple and gate code in system c and i am using vcs tool. could you please advice me that how do i complie this code, i follow these step to compile system c code on my tool:

1. syscan filename.cpp

2. vcs  -sysc filename.cpp

3. ./simv

 

#include "systemc.h"

SC_MODULE(and_a) {

 sc_in < sc_uint <8> > a, b;

 sc_out < sc_uint <8> > f;

 sc_in <bool> clk;

 void comp_and()
 {

  f.write(a.read() & b.read());

  }

 SC_CTOR(and_a) {

  SC_METHOD( comp_and );

  sensitive << a << b;
  }

};

After compilation i got this error message:
Parsing design file 'csrc/sysc/simv/top.v'
Top Level Modules:
       sYsTeMcToP
       sc_main
TimeScale is 1 ns / 1 ps
Starting vcs inline pass...
2 modules and 0 UDP read.
    However, due to incremental compilation, no re-compilation is necessary.
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv   -m32 -m32 -rdynamic -Wl,-rpath=/usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib -L/usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib -L/usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib/cosim/sysc231-gcc4 -L/usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib -rdynamic -Wl,-E    -Wl,-whole-archive    -lvcsucli -Wl,-no-whole-archive  /home/avnita/Workspace/SYSTEM_C_FILES/csrc/sysc/sysc_globals.o /usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib/ucli_sysc.o   objs/GdI28_d.o objs/amcQw_d.o amcQwB.o objs/ivVCS_d.o    SIM_l.o      rmapats_mop.o rmapats.o rmar.o rmar_nd.o  rmar_llvm_0_1.o rmar_llvm_0_0.o     /home/avnita/Workspace/SYSTEM_C_FILES/csrc/sysc/and_a.o /home/avnita/Workspace/SYSTEM_C_FILES/csrc/sysc/libcsrc_sysc_stubs.a    -lzerosoft_rt_stubs -lvirsim -lerrorinf -lsnpsmalloc -lvfs -lsysctli -lbfSim -lbfCbug -lsystemc231-gcc4 -lvirsim     -lvcsnew -lsimprofile -luclinative /usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib/vcs_tls.o          _vcs_pli_stub_.o   /usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib/vcs_save_restore_new.o /usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib/ctype-stubs_32.a -ldl -lm  -lc -lpthread -ldl
/usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib/cosim/sysc231-gcc4/libbfSim.a(bf_main.o): In function `bf_main':
bf_main.cpp:(.text+0x1289): undefined reference to `sc_main'
/usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib/cosim/sysc231-gcc4/libbfSim.a(bf_deltasync.o): In function `vcs_systemc_main':
bf_deltasync.cpp:(.text+0xda2): undefined reference to `sc_main'
/usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib/cosim/sysc231-gcc4/libbfSim.a(bf_deltasync.o): In function `vcs_systemc_elab':
bf_deltasync.cpp:(.text+0x42c9): undefined reference to `sc_main'
bf_deltasync.cpp:(.text+0x4746): undefined reference to `sc_main'
/usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib/cosim/sysc231-gcc4/libbfSim.a(bf_init.o): In function `gSyscMain':
bf_init.cpp:(.text+0x287): undefined reference to `sc_main'
/usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib/cosim/sysc231-gcc4/libbfSim.a(bf_scmt.o):bf_scmt.cpp:(.text+0x3c5): more undefined references to `sc_main' follow
collect2: error: ld returned 1 exit status
make: *** [product_timestamp] Error 1
Make exited with status 2
CPU time: .091 seconds to compile + .149 seconds to elab + .717 seconds to link

Could you please advice me that how i resolve this error and is any error is there in code. Please provide some code writing skills so I can improve.

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4 hours ago, David Black said:

As the error message says, you are missing the required sc_main subroutine. You did not show your invocation line, which could be helpful.

VCS invokes g++ automatically.  But this is correct, sc_main is missing. 

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I have written test bench for the above code (and gate) but i am getting some errors. Please guide me that how to write test bench in system C

#include "systemc.h"
#include "and_a.cpp"
SC_MODULE (and_tb) {
sc_in <sc_int <8> > a, b;
sc_out <sc_int <8> > f;
sc_in <bool> clk;
void and_gate() {
a.read(0);
b.read(0);
//f.write(0);
wait();
a.read(1);
b.read(1);
//f.write(1);
wait();
a.read(0);
b.read(1);
//f.write(0);
wait();
a.read(1);
b.read(0);
//f.write(0);
wait();
sc_stop();
}
SC_CTOR (and_tb) {
 SC_METHOD (and_gate);
  sensitive << clk.pos();
 }
};

Output: error message:

/usr/synopsys/vcs/N-2017.12-SP2-7/include/systemc231/sysc/communication/sc_signal_ports.h:201:22: note:   candidate expects 0 arguments, 1 provided
/home/avnita/Workspace/SYSTEM_C_FILES/and_tb.cpp:21:9: error: no matching function for call to ‘sc_core::sc_in<sc_dt::sc_int<8> >::read(int)’
 b.read(0);
         ^
/home/avnita/Workspace/SYSTEM_C_FILES/and_tb.cpp:21:9: note: candidate is:
In file included from /usr/synopsys/vcs/N-2017.12-SP2-7/include/systemc231/sysc/communication/sc_clock_ports.h:31:0,
                 from /usr/synopsys/vcs/N-2017.12-SP2-7/include/systemc231/systemc_:54,
                 from /usr/synopsys/vcs/N-2017.12-SP2-7/include/systemc231/systemc:2,
                 from /usr/synopsys/vcs/N-2017.12-SP2-7/include/systemc231/systemc_.h:245,
                 from /usr/synopsys/vcs/N-2017.12-SP2-7/include/systemc231/systemc.h:2,
                 from /home/avnita/Workspace/SYSTEM_C_FILES/and_tb.cpp:1:
/usr/synopsys/vcs/N-2017.12-SP2-7/include/systemc231/sysc/communication/sc_signal_ports.h:201:22: note: const data_type& sc_core::sc_in<T>::read() const [with T = sc_dt::sc_int<8>; sc_core::sc_in<T>::data_type = sc_dt::sc_int<8>]
     const data_type& read() const
                      ^
/usr/synopsys/vcs/N-2017.12-SP2-7/include/systemc231/sysc/communication/sc_signal_ports.h:201:22: note:   candidate expects 0 arguments, 1 provided
gmake: *** [and_tb.o] Error 1

 

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Hello sir, I wrote and_gate systemc code with test bench and it got compiled, also generated simv but it shows Segmentation fault (core dumped) error. Could you please suggest me what exactly it is and how I will resolve this.

  • #include "systemc.h"
  •  //AND gate module
  •  SC_MODULE (and_gate) {
  •   sc_in <bool> a, b;
  •   sc_out <bool> c;
  •  //Process for AND gate
  •    void and_fun() {
  •      c.write(a.read() & b.read());
  •     }
  •  //Constructor for AND gate module
  •    SC_CTOR (and_gate) {
  •     SC_METHOD (and_fun);
  •  //process for sesitivity
  •     sensitive << a << b;
  •     }
  •  };
  •  //Testbench for AND gate
  •    int sc_main (int argc, char* argv[]) {
  •  //testbench signals
  •    sc_signal <bool> a, b, c;
  •    sc_trace_file *tf;
  •  //module instantiation and name based connection
  •     and_gate and1 ("and_gate_and1");
  •       and1.a(a);
  • and1.b(b);
  •       and1.c(c);
  •     tf->set_time_unit(1, SC_NS);
  •  a = 0;
  •  b = 0;
  •  wait();
  •  //sc_start(1.0, SC_NS);
  •  //a = 0;
  •  //b = 1;
  •  //wait();
  •  //sc_start(1.0, SC_NS);
  •  //a = 1;
  •  //b = 0;
  •  //sc_start(1.0, SC_NS);
  •  //a = 1;
  •  //b = 1;
  •  //sc_start(1.0, SC_NS);
  •  //sc_stop();
  • cout << "Finished at time " << sc_time_stamp() << endl;
  •  return 0;
  • }

[root@silicon SYSTEM_C_FILES]# vi and_gate.cpp
[root@silicon SYSTEM_C_FILES]# syscan and_gate.cpp
[root@silicon SYSTEM_C_FILES]# vcs -sysc and_gate.cpp
make: Entering directory `/home/avnita/Workspace/SYSTEM_C_FILES/csrc'
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv   -m32 -m32 -rdynamic -Wl,-rpath=/usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib -L/usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib -L/usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib/cosim/sysc231-gcc4 -L/usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib -rdynamic -Wl,-E    -Wl,-whole-archive    -lvcsucli -Wl,-no-whole-archive  /home/avnita/Workspace/SYSTEM_C_FILES/csrc/sysc/sysc_globals.o /usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib/ucli_sysc.o   objs/GdI28_d.o objs/amcQw_d.o amcQwB.o objs/ivVCS_d.o    SIM_l.o      rmapats_mop.o rmapats.o rmar.o rmar_nd.o  rmar_llvm_0_1.o rmar_llvm_0_0.o     /home/avnita/Workspace/SYSTEM_C_FILES/csrc/sysc/and_gate.o /home/avnita/Workspace/SYSTEM_C_FILES/csrc/sysc/libcsrc_sysc_stubs.a    -lzerosoft_rt_stubs -lvirsim -lerrorinf -lsnpsmalloc -lvfs -lsysctli -lbfSim -lbfCbug -lsystemc231-gcc4 -lvirsim     -lvcsnew -lsimprofile -luclinative /usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib/vcs_tls.o          _vcs_pli_stub_.o   /usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib/vcs_save_restore_new.o /usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib/ctype-stubs_32.a -ldl -lm  -lc -lpthread -ldl
../simv up to date
make: Leaving directory `/home/avnita/Workspace/SYSTEM_C_FILES/csrc'
[root@silicon SYSTEM_C_FILES]# ./simv -gui
Segmentation fault (core dumped)

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Hello sir,

Again it through an error messange for this code

 #include "systemc.h"

 //AND gate module
 SC_MODULE (and_gate) {
  sc_in <bool> a, b;
  sc_out <bool> c;

 //Process for AND gate
   void and_fun() {
     c.write(a.read() & b.read());
    }

 //Constructor for AND gate module
   SC_CTOR (and_gate) {

    SC_METHOD (and_fun);

 //process for sensitivity
    sensitive << a << b;
    }
 int sc_main(int argc, char* argv[]) {
  //return 0;
  }
};

/usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib/cosim/sysc231-gcc4/libbfSim.a(bf_main.o): In function `bf_main':
bf_main.cpp:(.text+0x1289): undefined reference to `sc_main'
/usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib/cosim/sysc231-gcc4/libbfSim.a(bf_deltasync.o): In function `vcs_systemc_main':
bf_deltasync.cpp:(.text+0xda2): undefined reference to `sc_main'
/usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib/cosim/sysc231-gcc4/libbfSim.a(bf_deltasync.o): In function `vcs_systemc_elab':
bf_deltasync.cpp:(.text+0x42c9): undefined reference to `sc_main'
bf_deltasync.cpp:(.text+0x4746): undefined reference to `sc_main'
/usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib/cosim/sysc231-gcc4/libbfSim.a(bf_init.o): In function `gSyscMain':
bf_init.cpp:(.text+0x287): undefined reference to `sc_main'
/usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib/cosim/sysc231-gcc4/libbfSim.a(bf_scmt.o):bf_scmt.cpp:(.text+0x3c5): more undefined references to `sc_main' follow
collect2: error: ld returned 1 exit status
make: *** [product_timestamp] Error 1
Make exited with status 2
CPU time: .106 seconds to compile + .017 seconds to elab + .665 seconds to link

 

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Sir i have an doubt that when i compile any code in system c it generate simv file and i simulate it by using ./simv command but then i wrote new code and complie it , it got compiled the previous code and and showing the same output as previous one. Also in my systemc directory location it generate /csrs directory and inside csrc it generate /sysc directory and inside this it automatically generate .o and .a extention file. Sir could you please advice me on this and guide me that how I will get clear view about systemc.

 

/home/avnita/Workspace/SYSTEM_C_FILES/csrc/sysc/half_adder.o: In function `sc_main':
half_adder.cpp:(.text+0x0): multiple definition of `sc_main'
/home/avnita/Workspace/SYSTEM_C_FILES/csrc/sysc/and_gate1.o:and_gate1.cpp:(.text+0x0): first defined here
collect2: error: ld returned 1 exit status
make: *** [product_timestamp] Error 1

 

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please advice me resolve this issue

Info: (I804) /IEEE_Std_1666/deprecated: multiple () binding deprecated, use explicit port binding instead.
Chronologic VCS simulator copyright 1991-2017
Contains Synopsys proprietary information.
Compiler version N-2017.12-SP2-7; Runtime version N-2017.12-SP2-7;  Nov 23 19:52 2019
at time15 ns::(a, b, cin):000(a, b, cin):00
simv: /home/avnita/Workspace/SYSTEM_C_FILES/adder_testbench.cpp:30: void testbench::process(): Assertion `COUT == SC_LOGIC_1' failed.

An unexpected termination has occurred in ./simv due to a signal: Aborted
Hostname silicon

 

Command line: ./simv

--- Stack trace follows:

Info: (I804) /IEEE_Std_1666/deprecated: multiple () binding deprecated, use explicit port binding instead.

Dumping VCS Annotated Stack:
#0  0xf7fd9430 in __kernel_vsyscall ()
#1  0xf230a3a3 in __waitpid_nocancel () from /lib/libc.so.6
#2  0xf228abbe in do_system () from /lib/libc.so.6
#3  0xf2553d5b in system () from /lib/libpthread.so.0
#4  0xf75baa30 in SNPSle_10ee25eff68cd8461c9146fa1d0b35e87067f3c8015b313e639d2928478c79b3f673f99203bcf8be64600612100082236bffb2007f1e0ef9 () from /usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib/liberrorinf.so
#5  0xf75bc286 in SNPSle_10ee25eff68cd8461c9146fa1d0b35e87067f3c8015b313efba706aab251478fa49e66610e453774633a6c152e7ef778f2202cda681f3d4e () from /usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib/liberrorinf.so
#6  0xf75b462d in SNPSle_d35ca1ff70d465c2b9b1a72eee90a506fdd009d3de3db1de () from /usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib/liberrorinf.so
#7  0xf4470a76 in SNPSle_64133461705005bb725549e2e6fa1b3f () from /usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib/libvcsnew.so
#8  0xf42aca24 in SNPSle_82244d58c54c18c70d63edc9becab634 () from /usr/synopsys/vcs/N-2017.12-SP2-7/linux/lib/libvcsnew.so
#10 0xf7fd9430 in __kernel_vsyscall ()
#11 0xf227b227 in raise () from /lib/libc.so.6
#12 0xf227ca63 in abort () from /lib/libc.so.6
#13 0xf22740a7 in __assert_fail_base () from /lib/libc.so.6
#14 0xf2274157 in __assert_fail () from /lib/libc.so.6
#15 0x0814e630 in testbench::process() ()
#16 0x083823ad in sc_core::sc_process_b::semantics (this=0x8552b98) at vcs_cbug_step_into.cpp:80
#17 0x0836d744 in sc_core::sc_thread_cor_fn(void*) ()
#18 0x0838253a in sc_cor_qt_wrapper ()
#19 0x08375906 in qt_align ()

Process VmPeak: 127900 kb, VmSize: 127896 kb
System Free Memory: 1348228 kb, System Free Swap: 8126460 kb

 

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As the error message says, you have a failing assertion in your testbench code in adder_testbench.cpp, line 30 (emphasis mine):

20 hours ago, Avnita said:

simv: /home/avnita/Workspace/SYSTEM_C_FILES/adder_testbench.cpp:30: void testbench::process(): Assertion `COUT == SC_LOGIC_1' failed.

There is not much we can do about this without knowing your testbench and your model.

Hope that helps,
   Philipp

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