Jump to content

UVM RAL implementation methodology for large designs


Recommended Posts

Hello,

I was wondering if are there any resources (papers, blogs, posts, best practices) about methodologies to implement UVM RAL for "large" designs (>100K registers and 50K rams)? I tried to do some research online but most of the results never cover "large" designs.

I have experience using RAL and doing some customisation to make it work in a particular environment (callbacks, maps, defining specialised registers, sequences) but most of them were "little" (1K regs and 100 rams)

I'm interested on any information about aspects such as:

  • Reg model re-usability and portability at sub-system and system level environments
  • Performance: How heavy is the register model, since having this much registers may have a huge performance penalty over simulations
  • Dynamic reconfiguration (I know in 1.2 once your model is locked not much can be done)
  • RAM modelling in RAL (since it the uvm_mem is different from uvm_reg)
  • Register Model Partitioning at block level
  • Register Model limitations on real projects usage
  • Implementation of different sized registers and non uniform mapping
  • General RAL limitations

Any material or hints on these topics is really appreciated
Apologies for the broad question

Thanks
-R

Link to post
Share on other sites
  • 2 weeks later...

Join the conversation

You can post now and register later. If you have an account, sign in now to post with your account.
Note: Your post will require moderator approval before it will be visible.

Guest
Reply to this topic...

×   Pasted as rich text.   Paste as plain text instead

  Only 75 emoji are allowed.

×   Your link has been automatically embedded.   Display as a link instead

×   Your previous content has been restored.   Clear editor

×   You cannot paste images directly. Upload or insert images from URL.

×
×
  • Create New...