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Help me! SV attributes application, who can tell me the usage of attributes? Thanks!


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Hi everyone:

I have a syntax problem when i read VMM source code. Here is the code segment:

(*_vcs_vmm_class=1*)
class vmm_sb_ds_registeration;
  bit is_in;
  bit is_out;
  vmm_sb_ds::ordering_eorder;
endclass
So, what's the meaning of the "(*_vcs_vmm_class=1*)", and why use it before the class vmm_sb_ds_registeration?

I looked for the IEEE 1800-2009, only konws the syntax above is attributes, but do not understand it's meaning, and how

to use it properly.

Could anyone tell me this question and give me a application example? Thanks a lot!

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hi,

This is the UVM forum and is not the appropriate place for VMM question.

1) Please post VMM questions on vmm forum at http://www.vmmcentral.org/forums

2) l assume you did a typo/copy-paste error as the code is not the same as VMM source. The source code is actually:

`ifdef VMM_SB_DS_IN_STDLIB
`include "sb/vmm_sb.sv"`ifdef VCS
(* _vcs_vmm_class = 1 *)
`endif
class vmm_sb_ds_registration;
  vmm_sb_ds_base        sb;
  bit                   is_in;
  bit                   is_out;
  vmm_sb_ds::ordering_e order;
endclass
`endif

3) there is nothing wrong with using verilog attributes, it is a mechanism that allows code to indicate attributes that tools can recognize and control their behaviour accordingly.

4) you have not stipulated what syntax error message you are encountering.

please use a more appropriate forum for such discussions.

-adiel.

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  • 1 month later...

Typically Verilog/SV attributes are used to provide tools (simulators, linters, debuggers, synthesizers etc.) with specifci "directions" - in the olden days they used to be done via "pragma-s", Verilog-2001 onwards it is done better via attributes. Usually "users" don't need to bother about them at all, and tose tools that don't understand such attributes can simply ignore them!

So long story short - as a "reader of VMM source code" - you can ignore that attribute.

HTH

Ajeetha, CVC

www.cvcblr.com/blog

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