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Verifying Verification Components


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I would do something I've previously done with SystemC (where uvm_error hails from). Basically, replaced the report handler with my own intercept to recategorize errors. Then added a mechanism to register "expected" errors, warnings, fatals. Prior to a point where an error was going to be injected, I would issue something like:

begin_expect_error( "packet failure", 2 );
inject_error( ... );
wait_for_appropriate_time_or_event();
end_expect_error( "packet failure" );

If the report handler sees up to two errors, I would change the message severity to INFO and count off the expected error. At the end_expect_error call, I would check that exactly the number of expected errors occurred or consider it an error. Also, have to consider the possibility of the end_ call never happening.

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Thanks for the reply David. This is similar do what has been done in SVUnit. They provide their own UVM reporter and redefine `uvm_error to call that instead. I was hoping that UVM already had a more built-in mechanism for intercepting messages. If so, I could simply put the intercepted messages in a queue, verify that the queue contains the messages I expect and then pass/fail the test accordingly. I have to dig deeper and learn more but I was hoping that there would be a UVM action I can use or maybe uvm_report_catcher which by the name of it sounds related. Maybe these concepts can't be used for what I'm trying to do? 

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