IPXACT for Registers alone for UVM RAL

[saravanan]

Hi All, 

I am working in verification. Where i have to generate reg_block for all the IP's using IPXACT. also top level reg_block which instantiates all the IP level register block using IPXACT. But i am not interested in  Ports/Businterface/component. Please advise me what is the best method to do it. 

 

Thanks

Saravanan

 

[kock]

Hello Saravan,
There are two options.

1. You create a single IP-XACT component that contains a memory map describing your whole system. So the address block base address + register offset represents the absolute base address of the register in your memory map. There is no need to describe bus interfaces is this approach. However, your IP-XACT component is not re-usable; it is a dedicated description of your current system.

2. Your create an IP-XACT component for each individual IP describing the registers for that IP. These IP-XACT components also need a bus interface referencing the component memory map. In these descriptions, the address block base address + register offset represents the base address offset of the register relative to the base address of an instance of such a component. Next, you create an IP-XACT design in which you instantiate your IP-XACT components. In addition you need to create IP-XACT components for (possible dummy) CPU and bus. You encode the system memory map using address spaces and bridges in the bus. The CPU holds the global address space. You connect all bus interfaces like this:

• CPU instance master interface -> BUS instance slave interface
• BUS instance master interface 1 -> IPx instance slave interface
• BUS instance master interface 2 -> IPy instance slave interface
• BUS instance master interface 3 -> IPz instance slave interface
• ...

Based on this design topology it is possible to compute the system memory map. This is typically supported by an IP-XACT Design Environment. All IP instance registers are mapped in the address space of the CPU using the addressing of the BUS. The result could be written out as a single IP-XACT component as described in Option 1. However, that result could also be written out as a UVM register model.

The advantage of Option 2 is that your IP-XACT component register descriptions of your IPs are reusable. The only thing you need to change between your current system and your next system is the BUS component (different #number of slave interfaces and different addressing) and the IP-XACT design instantiating the relevant IPs.

Please note that Option 2 is a simplistic representation of your system only for the purpose of describing the system memory map. However, you can refine this into an IP-XACT design hierarchy that represents the physical connectivity to capture the physical connectivity (wiring) as well as the logical connectivity (memory map) in a single IP-XACT design hierarchy (and hence single data model).

Also note that you can apply Option 2 without creating the IP-XACT design and IP-XACT components CPU and BUS if you write the top-level UVM block manually which instantiates the generated IP UVM register models with the correct base addresses.

Best regards,
Erwin