Jump to content
mzio

Clock sharing seg fault insert_parent(int)

Recommended Posts

I have a hierarchical design and I have a problem with the clock signal.

Consider top module A where the clock is generated, a module B inside of it with sc_in<bool> clk port bound to sc_clock signal.

Inside of module B I instantiate other modules, some of them with sc_in<bool> clk port.

When I try to connect the clock port of the modules inside B I get a segmentation fault, that's gdb output: 

Thread 2 "ctrl_interface" received signal SIGSEGV, Segmentation fault.
[Switching to Thread 0x7ffff6789700 (LWP 23216)]
0x000000000042bb93 in sc_core::sc_port_base::insert_parent(int) ()

During the debug, if I remove the clock port of the modules inside B I don't get any segmentation fault.

Every clock port in this hierarchical design is sc_in<bool>, not sc_in_clk.

Any suggestions?

Share this post


Link to post
Share on other sites

Join the conversation

You can post now and register later. If you have an account, sign in now to post with your account.
Note: Your post will require moderator approval before it will be visible.

Guest
Reply to this topic...

×   Pasted as rich text.   Paste as plain text instead

  Only 75 emoji are allowed.

×   Your link has been automatically embedded.   Display as a link instead

×   Your previous content has been restored.   Clear editor

×   You cannot paste images directly. Upload or insert images from URL.


×
×
  • Create New...