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UVM register access with multiple masters to same register model


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You need to provide more detail.

Like, why do you currently have to select one at compilation time?

What exactly do you mean by parallel access? Do you have 3 separate physical interfaces which can simultaneously access the same register?

Or as often the case, do you have 3 masters which can all access the same registers via a fabric and a single physical interface to the registers?

What are you using for your register model? RAL ( uvm_reg ) ?

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