What would be the strategy to verify

[karandeep963 8]

Hi ,

 

I have a case in which my DUT only toggles the valid bits of data output and doesn't change the rest of the bits. At the receiever side its state machine decides what all are the valid bits.

DUT is purely based on couple of state machines.

I have a C model for the same which does not have that state machines though it every time toggless all the data fields.

 

For an example , lets say DUT transmits 0101 at N cycles and has to transmit only 0x04 at N+1th cycle so it again transmits 0101. since the LSB is not valid in this case.

In case of model , it tries to follow the DUT and generated 0101 for Nth cycle and 0100 for N+1th cycles unlike DUT.

 

There is SV-UVM scoreboard which compares both the transactions and creeps for this case.

 

Now , I have few ideas in my mind.

1: I need to sit with designer and get to know the inside indepth working and re-write the stuff in scoreboard.

2: Other thing is I can do bitwise AND of DUT with MODEL output and compare with MODEL in scoreboard  , but this will fail for the case in which DUT always respond with 0xFFFF.

 

Any idea what can be the better approach in this case.

 

Thanks,

Karandeep

[tudor.timi 53]

It's not clear in this case what 'valid' means. I don't understand why in your case, when the model would generate '0100', the DUT will respond with '0101' after a '0101'.