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Generating constrained random pre-load file for SoC TB

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Hi All,


Any idea how to use UVM to generate a pre-load files using constrained random method for SoC verification.


Is it OK to have an UVM agent for this purpose which does not require any sequencer?


The idea here is to verify CPU execution which is based the flash pre-load file. 






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  • 1 month later...

You could use a file read task as body inside a sequence and let the regular ENV --> Agent --> SQR --> DRVR setup as-is. Yes your SQR is not really "sequencing" stuff, but an arbiter with just one req active is not as bad as it may sound!


However an alternate approach is to use a Test layer alone and get rid of other unwanted pieces of UVM layers to keep it simple. This is what we have seen some users do with our opensource Go2UVM package - see www.go2uvm.org for more details on this if interested.





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