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How can I use "randomize() with" along with "inside", on the same line?

 

Below is some code that solves the problem using >= and <=, but I'd like to use "inside".

module top;

class aclass;
   int index;

   function void get_latency;
      //assert (randomize(index) with {index inside {[1:5]}}) else begin  //WHAT IS THE PROPER SYNTAX?
      //assert (randomize(index) inside {[1:5]}) else begin               //WHAT IS THE PROPER SYNTAX?
      assert (randomize(index) with {index<=5;  index>=1;}) else begin    //WORKS
         $display("ERROR:  We failed!");
         $finish;
      end

      $display("RESULT: index=%0d",index);
   endfunction
endclass

   initial begin
      aclass a_class=new();
      a_class.get_latency();
      $finish;
   end
endmodule

I often grapple with the "randomize with" syntax, getting confused with squiggly brackets and semicolons, and refer to the LRM.  (Any tips that will stick in my head are welcome.)

 
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The syntax is

assert (
         randomize(index) with 
                               { index inside { [1:5] } ;  }  
       ) else begin

It's the same {} as if you wrote named constraint block. Each constraint within the {} needs to be terminated with a semi-colon

constraint range_constraint
                               { index inside { [1:5] } ;  } 

           

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  • 4 years later...

mastrick,

 Thanks for that.   That is a very good point. 
  For forums or any sort of Q&A I try to show the focus of the post as succinctly as possible.  Doing so, I sometimes use styles I wouldn't ordinarily, like skipping a "begin ... end" when it is not required because there is only one line of code.  (I like to always use begin/end and heavily use parentheses to be explicit.)
 I agree with your point.

 

Why am I responding to threads from 4 years ago, one might ask?   Because after 3 years of not using UVM and almost no SystemVerilog, I am trying to get the rust off by revisiting questions I've had in the past.  Yes, I was working at a place that favored vanilla Verilog, and where SystemVerilog was discouraged and UVM was not used.

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