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kkibria

Need Clarification on default value assignment for multidimensional component ports

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Hello folks:
 
I am referring to IP-XACT 1685-2014 standard, but may be applicable to earlier versions as well.
 
Component wire ports can have multiple drivers. The each driver has an optional range (section 6.12.10.1) which can only be one dimensional. This works alright for one dimensional ports. However the standard also allows for declaring multidimensional component ports with arrays (6.12.7.1) and vectors (6.12.8.1). How do I interpret the driver range within the context of multidimensional ports?
 
It seems like default value can be specified for a slice of an standard verilog port. One may use a list of ranges allow port default value to be broken into several mutually exclusive parts perhaps in a more meaningful way. On the other hand, it seems to me from the spec that the default value can not be specified for an arbitrary multi dimensional slice of a (system verilog) multi dimensional port. Is it a correct assumption?
 

I also thought of an interpretation. I am not sure if that was the real intent of the spec. Let me attempt describing using following examples.

 

Verilog:
[n:m] portname;
In this case we are clear what default value and range would do.

 

System Verilog:
[a:b][c:d]...[n:m] portname;
In this case we can think [n:m] portname as the base object, and other additional dimensions merely repeats the base object. Now if we interpret that we will have to apply the default value and range to all the base base objects the same way then it is consistent across the board.

 

It would be a great help if someone can clarify this for me. Thanks in advance.

 

-- Khan Kibria 

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Hi Mark:

 

In such case I need a bit more clarification. I will use the following example, let me know if my bit order assumptions are correct.

Lets say the port is [3:0][2:0][1:0] portname;

 

Example 1:

If the range is not specified then the width of the default value has to be 4x3x2 = 24.

Default value bit ordering, leftmost ---- rightmost

portname[3][2][1], portname[3][2][0], portname[3][1][1], portname[3][1][0] ---- portname[0][0][0]

 

Example 2:

If the range is specified = [2:1] then the width of the default value has to be 2x3x2 = 6.

Default value bit ordering, leftmost ---- rightmost

portname[2][2][1], portname[2][2][0], portname[2][1][1], portname[2][1][0] ---- portname[1][0][0]

 

Regards,

-- Khan.

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