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I am trying to run the uvm builtin register sequences.   I seem to have broken our usage of them in porting code from a previous project.

 

Q1:  In the past, we've started them as default sequences.  Is there any way to have an error/warning appear if a 'set', such as the below, is never utilized (or 'get'-ed)? 



uvm_config_db#(uvm_object_wrapper)::set(this, "*.m_reg_agent.m_seq_reg.main_phase", "default_sequence", uvm_builtin_reg_test_seq::type_id::get());


I've added

uvm_top.print_topology();

and

uvm_config_db::dump();

and it seems the ::set should be working, but nothing is starting.

 

Q2:  Are builtin (base class) sequences automatically "::created" somehow/somewhere?   (Creation/new-ing is still necessary when you setup a default sequence, right?  Or is there some magic singleton-ness that happens?)

 

Q3: My error of the moment is as follows.  Your thoughts are appreciated.



UVM_FATAL @ 39990: reporter@@seq [SEQ] neither the item's sequencer nor dedicated sequencer has been supplied to start item in seq


always@(posedge clk),

ljepson74

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A1: You can start your simulation with the +UVM_CONFIG_DB_TRACE plusarg to see messages for set(...)/get(...) in the log file.

 

A2: You can have both use models. You can either tell the sequencer to start a sequence of a certain type by providing a type wrapper (like you did and the sequencer will instantiate it itself) or you can directly provide an instantiated sequence which you randomized/configured to your heart's desire (and the sequencer will start it). If you run your simulation with UVM_FULL (at least on the sequencer) you should see a message saying that it started the phase sequence and what type of sequence.

 

A3: This error comes from start_item(...) when it can't figure out on which sequencer to start it. If you aren't starting any sequences yourself, the seq name there for the sequence probably comes from the phase sequence which is getting started. I assume you have some problems with your register model configuration (something like a sequencer not being set for the register map). Also, these built in register sequences need a register or a register block to know what to access. I don't see how you can pass the phase sequence a reference to either on of these without creating an instance first, setting the register field and only then setting it as a phase sequence.

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I am trying to run the uvm builtin register sequences.   I seem to have broken our usage of them in porting code from a previous project.
 
Q1:  In the past, we've started them as default sequences.  Is there any way to have an error/warning appear if a 'set', such as the below, is never utilized (or 'get'-ed)? 
uvm_config_db#(uvm_object_wrapper)::set(this, "*.m_reg_agent.m_seq_reg.main_phase", "default_sequence", uvm_builtin_reg_test_seq::type_id::get());
I've added
uvm_top.print_topology();
and
uvm_config_db::dump();
and it seems the ::set should be working, but nothing is starting.
 
Q2:  Are builtin (base class) sequences automatically "::created" somehow/somewhere?   (Creation/new-ing is still necessary when you setup a default sequence, right?  Or is there some magic singleton-ness that happens?)
 
Q3: My error of the moment is as follows.  Your thoughts are appreciated.
UVM_FATAL @ 39990: reporter@@seq [SEQ] neither the item's sequencer nor dedicated sequencer has been supplied to start item in seq
always@(posedge clk),
ljepson74

 

 

 

this sounds like a bug. normally the sequence and/or items do know on which sequencer they run on *or should run on". there are a few situations where that in of is/was missing. a recent issue i remember was one where when an item was sent to a low level bfm sequencer from a virtual sequence running on a null sequencer then the sequencer info was wrong leading to similar fails..

 

 

/uwe

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