Jump to content

Integratinc specman eVC in systemC test bench


Recommended Posts

Hi All,

I need help in integrating specman eVC in systemC based TB.

Does anyone know how to do this?

 

Also please let me know how to control specman eVC sequence from systemC testcase?

 

Note: I am using incisive tools for systemC TB compilations and simulation.

 

Thanks in advance.

Mani

Link to post
Share on other sites

The standardization of SCV and UVM-SystemC in Accellera do not cover integration of eVC.

 

I suggest you ask your EDA tool supplier on the capabilities to support this, since you need to have an simulator supporting the e language (IEEE1647). A possible solution could be UVM-ML :

http://forums.accellera.org/files/file/65-uvm-ml-open-architecture/

Link to post
Share on other sites

Archived

This topic is now archived and is closed to further replies.

×
×
  • Create New...