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SC_FIXED and UVM ML Packer


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Hi,

I am trying to use SC_FIXED in a UVM ML environment, but the uvm_packer.h doesn't support sc_fixed.

  virtual uvm_packer& operator << (bool a);
  virtual uvm_packer& operator << (char a);
  virtual uvm_packer& operator << (unsigned char a);
  virtual uvm_packer& operator << (short a);
  virtual uvm_packer& operator << (unsigned short a);
  virtual uvm_packer& operator << (int a);
  virtual uvm_packer& operator << (unsigned int a);
  virtual uvm_packer& operator << (long a);
  virtual uvm_packer& operator << (unsigned long a);
  virtual uvm_packer& operator << (long long a);
  virtual uvm_packer& operator << (unsigned long long a);
 
  virtual uvm_packer& operator << (std::string a);
  virtual uvm_packer& operator << (const char*);
 
  virtual uvm_packer& operator << (uvm_object* a);
  virtual uvm_packer& operator << (const uvm_object& a);
  virtual uvm_packer& operator << (const sc_logic& a);
  virtual uvm_packer& operator << (const sc_bv_base& a);
  virtual uvm_packer& operator << (const sc_lv_base& a);
  virtual uvm_packer& operator << (const sc_int_base& a);
  virtual uvm_packer& operator << (const sc_uint_base& a);
  virtual uvm_packer& operator << (const sc_signed& a);
  virtual uvm_packer& operator << (const sc_unsigned& a);
  template <class T>

Any idea how to solve it?

Thanks

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  • 2 weeks later...

Hi Matteo,

 

SystemC's sc_fixed cannot be packed 'as is' since the '<<' operator is not defined to support it.

However, you can bypass this limitation by using the following workaround.

Cast the sc_fixed to a variable of type ‘double’ (64 bits), and then pack it as two integers (each with 32 bits).

This can be achieved by using a union of one double and two ints.

The same could be done for unpacking, as can be seen in this example:

 

class packet : public uvm_object {

public:

  int data;

  sc_fixed<5,3> fixed;

 

virtual void do_pack(uvm_packer& p) const {

    union ir_tag {

            double d;

            int ints[2];

        } my_ir;

       my_ir.d = fixed.to_double();

      p << data << my_ir.ints[0] << my_ir.ints[1];

  }

  virtual void do_unpack(uvm_packer& p) {

    union ir_tag {

      double d;

      int ints[2];

    } my_ir2;

 

    p >> data;

    p >> my_ir2.ints[0];

    p >> my_ir2.ints[1];

    fixed = sc_fixed<5,3>(my_ir2.d);

  }

}

 

In the SystemVerilog side , the equivalent of SC’s double is ‘real’, so you would need to define it in SystemVerilog as follows

(nake sure you define use the `uvm_field_real macro for the real type.

 

class packet extends uvm_transaction;

   int    data;

   real fixed;

  

   `uvm_object_utils_begin(packet)

      `uvm_field_int(data, UVM_ALL_ON)

      `uvm_field_real(fixed, UVM_ALL_ON)

   `uvm_object_utils_end

….

Endclass //packet

 

 

Note - when you send a double from SystemVerilog to SystemC, and you cast it to a sc_type like 

what i did above, you will loose data, as the double type can contain much more information than the sc_fixed i defined. this is why extra caution should be applied in this direction.

 

 

Best regards,

 

Yuval Gilad   |   support_uvm_ml@cadence.com

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Hi Yuval,

thank you very much for your reply.

 

I came up with a similar solution by converting the sc_fixed to an integer and packing it, but yours it is more elegant.

I don't need to send data from the SV to the SC, so I ignored the do_unpack.

 

Best Regards

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