Jump to content
commandos

about uvm_reg::add_hdl_path_slice,can I assign a hdl varible declared as "wire""

Recommended Posts

Hi,

In rtl design, I have a wire [3:0] d signal. It's assigned with 4 signals declared as reg type.

So my question is when I try to add hdl path slice for d what should I do?

I tried to add each of the four signals as slices, then in the test backdoor write to d has problem, I can't seem to pass wdata well.

Ex: env. rm. d. write(...UVM_BACKDOOR) doesn't work.

The d is a register naming which I create a uvm reg for it.

Any input is appreciated.

Share this post


Link to post
Share on other sites

The problem is that a wire can only be driven with hld_force. The register model assumes they are modeled as regs. You did not indicate how the regs were connected to the wire, but it probably doesn't matter. SystemVerilog allows a single process to assign a reg that is connected to a wire from within a module; however, if more than a single process is involved (e.g. the register model), then wire/assign semantics follow. I suspect that is your problem. If you care to post an example of your modules and how the reg's/wire's are connected and driven, we could confirm this.

Share this post


Link to post
Share on other sites

Sorry that I did not post the example. Here it is:
Hierarchy of design:
top.dut.u_reg

module u_reg;
...

output [31:0] d_o,

...
wire [31:0] d;
reg a_reg;
reg b_reg;
reg c_reg;
reg d_reg;

 

//Each *_reg has a driver block for updating its value
//there are a few combination logic outside always block
//Ex:
always (posedge clk or negedge rst_n) begin
 if (!rst_n)
   a_reg = 0;
else if (we_n)
  a_reg ‹= a_reg_nxt;
end
decode and value calculation for a_reg here.
...

assign d = {28'h0,a_reg, b_reg,c_reg,d_reg};

//d is the register, and there is a output from this module, d_o:
assign d_o = d;

endmodule

I tried to use the following coeds in my reg_block,

the d register has objcet name: D_reg:

 
   D_reg.add_hdl_path_slice("d", 0, 32);
   D_reg.add_hdl_path_slice("a_reg", 3, 1);
   D_reg.add_hdl_path_slice("b_reg", 2, 1);
   D_reg.add_hdl_path_slice("c_reg", 1, 1);
   D_reg.add_hdl_path_slice("d_reg", 0, 1);
 
The simulation log does show that the simulation(questasim) can resolve the hdl path, but the write data couldn't get through. The waveform dose not indicate the data changes either.
 
Thanks.

Share this post


Link to post
Share on other sites

Join the conversation

You can post now and register later. If you have an account, sign in now to post with your account.
Note: Your post will require moderator approval before it will be visible.

Guest
Reply to this topic...

×   Pasted as rich text.   Paste as plain text instead

  Only 75 emoji are allowed.

×   Your link has been automatically embedded.   Display as a link instead

×   Your previous content has been restored.   Clear editor

×   You cannot paste images directly. Upload or insert images from URL.


×
×
  • Create New...