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ljepson74

Use objections in uvm phase functions? (or just tasks)

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True.

 

Objections are used as an end-of-test mechanism, to make sure that the simulation doesn't stop prematurely. The flow of execution in a UVM simulation goes through all of the phases anyway, so objections are only useful to make sure that the run_phase (or its sub-phases) don't end too early.

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Because it makes no sense. In Verilog/SystemVerilog, functions cannot block and take 0 time. An objection to ending a phase means extending the time of that phase. If you extend the time in the "build_phase", there is nothing you could add to it.

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Thanks a lot.
I didn't realize that an objection to ending a phase meant extending the time only.  I thought the lack of an objection might mean that the phase could end anytime, even between delta cycles at the same time.  (I'm not sure if delta cycle is the proper term there.)
 
So, all functions that are called at the start of one of the uvm run phases (before any time consuming events) will be guaranteed to complete.
And any uvm run phase which has no time consuming elements needs no objections.
Right?
(I'm not saying I have a reason for such measures.  I am just checking.)
 
 
thanks again for spelling it out for me
 
 
Perhaps it's just me, but I don't think the uvm_users_guide_1.1.pdf is clear enough about this.  "each phase" to me means "every phase".  (see below)
Also, I didn't read "activity" below as meaning something that consumes time.
 

snippet from uvm_users_guide_1.1.pdf:

3.11 Managing End of Test
UVM provides an objection mechanism to allow hierarchical status communication among components.
There is a built-in objection for each phase, which provides a way for components and objects to
synchronize their testing activity and indicate when it is safe to end the phase and, ultimately, the test.
In general, the process is for a component or sequence to raise a phase objection at the beginning of an
activity that must be completed before the phase stops and to drop the objection at the end of that activity.
Once all of the raised objections are dropped, the phase terminates.

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SystemVerilog functions consume no time. The concept of a delta cycle doesn't even come into consideration.

All non-task based phases (i.e. FUNCTIONS) are by definition happening in zero time.

In the default setup, there are four non-task based phases that execute at time zero (i.e. directly after 'initial begin'); however, they also execute in a very specific order:

  • build_phase
  • connect_phase
  • end_of_elaboration_phase
  • start_of_simulation_phase

For all components, their individual build_phase's all execute to completion before any connect_phase is executed. The order in which build_phases occur between components is top-down.

Once build_phase is complete, there is no going backwards and the connect_phase begins. Similar to build_phase, all components execute their connect_phase before moving to the next phase.

 

When all of those startup non-task based phases have completed in the stated order, then the task-based phases begin. They consume time (usually) and their order can be quite different depending on their domain. See a paper by John Aynsley presented at the recently completed San Jose DVCon 2015 on the topic for more information. You will soon be able to find and view it on the Doulos web site under the KnowHow section for SystemVerilog/UVM.

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