ljepson74 10 Posted March 3, 2015 Report Share Posted March 3, 2015 What tools exist for SystemVerilog/UVM linting? I recently evaluated AMIQ's Verissimo (which I liked). However, I'd like to know what else is out there. Quote Link to post Share on other sites
tudor.timi 53 Posted March 3, 2015 Report Share Posted March 3, 2015 If you're a Cadence user you get HAL (HDL Advanced Linter I guess it's called, but don't let the name fool you, it can do HVLs too) included with Incisive. Quote Link to post Share on other sites
sri.cvcblr 3 Posted January 7, 2016 Report Share Posted January 7, 2016 I know I am late to respond here, but we have a new start-up named VerifWorks (http://www.verifworks.com) that targets similar thing. We do have a SV, SVA & UVM linter built on top of a Python API provided by Invionics (http://www.invonics.com), however we also have a native DVRules product that is in early Beta now that works via reflection API natively with simulator of your choice. Strictly speaking DVRules (native) is "rule checker" than a linter (as in parsing level). More details soon @ our Web site. Please do contact me offline if interested. Warm Regards Srini Quote Link to post Share on other sites
DavidLarson 0 Posted November 16, 2016 Report Share Posted November 16, 2016 I'm going through the HAL documentation and it looks l like the only languages that HAL supports are: Verilog, VHDL, SystemC and e. No system verilog. Rats. Quote Link to post Share on other sites
uwes 20 Posted January 17, 2017 Report Share Posted January 17, 2017 sv should be supported too in hal. typically hal is more focused on rtl code. /uwe Quote Link to post Share on other sites
rgarciaf071 1 Posted September 9, 2019 Report Share Posted September 9, 2019 I was wondering if there is up to this date any linter for UVM / SV non-RTL code besides verissimo it seems Cadence's HAL is not supporting several non-RTL constructs -R Quote Link to post Share on other sites
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